Curtiss-Wright FibreXtreme SL240, Hardware Reference Manual

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REGISTER SET
Receive Transaction CSR (TNS_CSR0) – Offset 0x60
Field Description Access Reset
Value
0 Interrupt Enable – Set to ‘1’ to enable an interrupt on
this transaction. Set to ‘0’ for normal operation. R/W 0
1 Skip entry – Skips to the next entry when this bit is set.
Set to ‘1’ to enable. Set to ‘0’ for normal operation. R/W 0
2 /SYNC status – status of the /SYNC line to the
controller. R 0
3 Link error status – status of the link error line to the
controller. ‘1’ = error, ‘0’ = no error. R 0
4 Abort & Writeback on /SYNC – Set to ‘1’ to abort the
current transaction and write the status back to the
transaction entry in memory on /SYNC. Set to ‘0’ not to
abort. R/W 0
5 Abort & Writeback on Link Error – Set to ‘1’ to abort the
current transaction and write the status back to the
transaction entry in memory on Link Error. Set to ‘0’ not
to abort. R/W 0
9 to 6 Reserved. None 0
10 Received SYNC without DVALID. R 0
11 Received SYNC with DVALID. Convert SYNC must be
enabled in the Link Control register for this bit to be
valid. R 0
31 to
12
Reserved. None 0
Receive Transaction Length (TLENGTH0) – Offset 0x64
Field Description Access Reset
Value
31 to 0 Transaction length in 32-bit words. R/W 0
Receive Chain PMC Address (CPCIADDR0) – Offset 0x70
Field Description Access Reset
Value
3 to 0 Reserved (Lower four bits of PMC address must be
zero). None 0
31 to 4 PMC address for the buffer to receive. R/W 0
Copyright 2006 B-15 FibreXtreme Hardware Reference Manual