Curtiss-Wright FibreXtreme SL240, Hardware Reference Manual

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OPERATION
4.4.3 Receiver/Transmitter Enable
The transmitter-enable and receiver-enable bits in the Link Control register turn off the
transmit and receive Serial FPDP data streams, respectively. Neither affects the loop
operation, so data will still be retransmitted if the loop operation is enabled. This makes
these options useful for record/playback systems where you wish to merely retransmit the
data received without processing it. The receive-enable is useful for disabling the receive
FIFO for the master in loop operation so that the data sent is not received.
4.4.4 CRC Generation/Checking
The CRC Generation/Checking option allows the SL240 card to detect data transmission
errors. The card is not capable of correcting the errors. Error correction is left to
application level design.
A single bit controls both generation and checking. CRC should be used in almost all
applications. It offers excellent coverage of data errors and has very little impact on link
throughput for maximum frame sizes. The option of disabling CRC is only retained for
compatibility with older third-party devices. Both nodes on the link (or all nodes in a loop
configuration) should be set to a common CRC mode or the resulting mismatch will
cause data errors and/or link errors.
4.4.5 Stop on Link Error or /SYNC
There are two DMA stop conditions available to the user—stop on link error and stop on
/SYNC. The stop on link error stops the DMA engine from removing data from the
receive FIFO when there is a link error, such as the link going down. The stop on /SYNC
option allows you to stop data from being received from the receive FIFO when a /SYNC
without /DVALID is received on the output.
4.4.6 Receive FIFO Threshold Interrupt
NOTE : The Receive FIFO Threshold Interrupt is not supported in the current revision
of the software. However, it may become available in a future revision.
SL240 cards can be configured to interrupt the host when the FIFO passes a certain
threshold, allowing for efficient PIO transactions out of the receive FIFO. This is
particularly important on data storage systems, where you do not want to remove data
from the FIFO until you have a full block of data to transmit. Select one of four different
thresholds through the control registers as follows:
•
Not empty
•
FIFO ¼ full
•
FIFO ½ full
•
FIFO ¾ full
Copyright 2006 4-5 FibreXtreme Hardware Reference Manual