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Curtiss-Wright FibreXtreme SL240, Hardware Reference Manual

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FOREWORD 

The information in this document has been carefully checked and is believed to be accurate; however, no 
responsibility is assumed for inaccuracies. Curtiss-Wright Controls, Inc. reserves the right to make changes 
without notice. 
 
Curtiss-Wright Controls, Inc. makes no warranty of any kind with regard to this printed material, 
including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. 
 
©Copyright 2006 Curtiss-Wright Controls, Inc., All rights reserved.  
SL240 Dual-Port Memory FIFO U.S. Patent #6,259,648. 
 
 

®

 is a registered trademark of Curtiss-Wright Controls, Inc. 

®

is a registered trademark of Curtiss-Wright Controls, Inc. 

®

 is a registered trademark of Curtiss-Wright Controls, Inc. 

 

Any reference made within this document to equipment from other vendors does not constitute an 
endorsement of their product(s). 
 
Published: February 28, 2006 
 
 
 
 
 
 
 
 
 
 
 
 
 

Curtiss-Wright Controls, Inc. Embedded Computing

Data Communications

 

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Paramount Place Suite 200

 

  

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Summary of Contents for FibreXtreme SL240

Page 1: ... SL240 Hardware Reference for Conduction Cooled PMC Cards Document No F T MR S2PMCCC A 0 A4 ...

Page 2: ......

Page 3: ...r a particular purpose Copyright 2006 Curtiss Wright Controls Inc All rights reserved SL240 Dual Port Memory FIFO U S Patent 6 259 648 is a registered trademark of Curtiss Wright Controls Inc is a registered trademark of Curtiss Wright Controls Inc is a registered trademark of Curtiss Wright Controls Inc Any reference made within this document to equipment from other vendors does not constitute an...

Page 4: ...th other radio and communication devices The user may be in violation of FCC regulations if this device is used in other than the intended market environments CE As a component part of another system this information technology product has no direct function and is therefore not subject to applicable European Union directives for Information Technology equipment ...

Page 5: ...5 1 Typical Topologies 2 8 2 5 2 Point to point 2 8 2 5 3 Chained 2 9 2 5 4 Single Master Ring 2 10 2 5 5 Multiple Master Ring 2 11 3 INSTALLATION 3 1 3 1 Overview 3 1 3 2 Unpack the Cards 3 1 3 3 Inspect the Cards 3 1 3 3 1 SL240 CCPMC Card 3 1 3 4 Connect the Cables 3 2 3 4 1 Transmission Media 3 2 3 4 2 Fiber Optic Cables 3 2 3 5 Troubleshooting 3 3 4 OPERATION 4 1 4 1 Overview 4 1 4 2 Theory o...

Page 6: ... CCPMC LEDs LU LS R1 R0 T1 and T0 2 4 Figure 2 3 Typical Applications of FibreXtreme SL240 in Advanced DSP Systems 2 6 Figure 2 4 FibreXtreme SL240 Extending FPDP 2 7 Figure 2 5 Point to Point Topology 2 8 Figure 2 6 Chained Topology 2 9 Figure 2 7 Single Master Ring 2 10 Figure 2 8 Multiple Master Ring 2 11 Figure 3 1 Fiber optic Simplex LC Connector 3 2 Figure 3 2 Fiber optic Duplex LC Connector...

Page 7: ...inators or highly skilled network users with at least a systems level understanding of general computer processing memory and hardware operation 1 1 3 Style Conventions Called functions are italicized For example OpenConnect Data types are italicized For example int Function parameters are bolded For example Action Path names are italicized For example utility sw cfg File names are bolded For exam...

Page 8: ...hannel Physical and Signaling Interface 3 FC PH 3 Revision 8 6 April 1996 Produced by the ANSI X3T11 standards group Front Panel Data Port Specifications ANSI VITA 17 1998 Revision 1 0 February 11 1999 Produced by the VITA Standards Organization IEC 825 1984 Radiation Safety of Laser Products Equipment Classification Requirements and User s Guide 2 parts 1993 LinkXchange LX2500 Physical Layer Swit...

Page 9: ...eet the needs of our customers suppliers and other stakeholders Provide our employees with the tools and overall work environment to fulfill maintain and improve product and service quality Ensure our customer and other stakeholders that only the highest quality product or service will be delivered The British Standards Institution BSI the world s largest and most respected standardization authori...

Page 10: ...ms or issues this document does not satisfactorily cover Our goal is to offer a combination of products and services that provide complete easy to use solutions for your application If you have any technical or non technical questions or comments contact us Hours of operation are from 8 00 a m to 5 00 p m Eastern Standard Daylight Time Phone 937 252 5601 or 800 252 5601 E mail DTN_support curtissw...

Page 11: ...via the PCI bus The PCI bus is used in most standard PCs and the PMC format is used in most popular single board computers CompactPCI is a 3U or 6U Euro card format PCI card designed as a more mechanically robust alternative to desktop PCI cards The FPDP versions of the card provide this interface through a simple unidirectional parallel port This port can be connected to existing FPDP equipment o...

Page 12: ...est Status LED that reports link stability Loop operation with out of band arbitration or point to point operation Provides a register set designed for easy programming and status retrieval 64 bit operation is backward compatible to 32 bit 33 MHz SL240 66 MHz PCI support 3 3 V signaling only in PMC form factor 128 MB Receive FIFO 1 KB Transmit FIFO Meets rugged level 2 specifications 2 2 1 SFF Med...

Page 13: ...nnel 1 is selected Channel 0 is not used Link Up LU The Link Up LED turns on when the SL240 is receiving a valid signal Signal Detect R0 R1 The Signal Detect LED R1 indicates a signal is being received by channel 1 of the transceiver LED R0 is not used Laser Enable T0 T1 The Laser Enable LED T1 indicates the channel 1 transceiver is turned on LED T0 is not used Figure 2 2 SL240 CCPMC LEDs LU LS R1...

Page 14: ...ard 48 IEEE 1394b Firewire copper media ports per IEEE 1394b port card Port cards and pluggable transceivers may be mixed in one system Supports Loop Point to Point One to Many communication links Supports multiple physical media options including short wavelength 850 nm long wavelength 1300 nm and HSSDC2 Automatic port fault isolation Front panel indicators Signal Detect indicator Transmitter ON ...

Page 15: ...ughput data transfer applications Figure 2 3 shows one example This figure shows the SL240 s usable data throughput rate 247 MBps PMC PMC 247 MBps Sensors Scan the Image DSP Systems Develop the Image High Performance General Purpose Computers Analyze the Image High Speed Storage Radar IR Sonar Acoustic Photon Video Etc 247 MBps 247 MBps 247 MBps 247 MBps SL240 Fibre Channel FULL FC 4 FIBRE CHANNEL...

Page 16: ...etaining simplicity high bandwidth and reliability This concept is shown in Figure 2 4 The type of transceiver used determines the distance the FPDP cards can be separated See section 2 2 1 Media Options for details on transceivers Using fiber optics provides electrical isolation ADC DSP SL240 FPDP FPDP SL240 SL240 150 m maximum SL240 Figure 2 4 FibreXtreme SL240 Extending FPDP Copyright 2006 2 7 ...

Page 17: ...low control is used the transmitter on each end will not transmit when the remote receiver is telling it to back off or the receive fiber is missing In this mode the maximum amount of data that can be transferred is 247 MBps per direction in this case both cards are receiving and transmitting 247 MBps at the same time The maximum distance between the nodes is 26 km There are many applications for ...

Page 18: ...tance between the nodes is limited only by the transceivers used 150 m maximum This topology is good for broadcasting data to multiple destinations where late data is of no use such as video transmission applications RX TX RX TX RX TX RX TX SL240 Card SL240 Card SL240 Card SL240 Card Figure 2 6 Chained Topology Copyright 2006 2 9 FibreXtreme Hardware Reference Manual ...

Page 19: ...h available from Curtiss Wright Controls Inc Software controls mastership switching of the ring There are rules associated with master switching listed in the Programming Interface section The flow control used in this case is similar to a multi drop FPDP bus where any receiver can back the transmitter off This is the typical configuration for record playback systems where you have multiple signal...

Page 20: ...low control is not allowed in this topology for rings above two nodes and the data cannot be passed through masters unless control guarantees that there is at least one source only node on the ring and that no two masters will transmit at the same time Single master rings should temporarily become multiple master rings when switching loop masters RX TX RX TX RX TX RX TX SL240 Card Master A SL240 C...

Page 21: ...ard and anti static bag from the carton 3 Place the bag on the anti static mat 4 Open the anti static bag and remove the card 5 In the unlikely event that you should need to return your SL240 card please keep the original shipping materials for this purpose Any optional equipment is shipped in separate cartons 3 3 Inspect the Cards The SL240 card consists of a single card with a built in link inte...

Page 22: ...t may not be possible to clean the connector out and could result in damage to the transmitter or receiver lens Hair dirt and dust can interfere with the light signal transmission Use an alcohol based wipe to clean the cable ends For short wavelength modules either a 50 µm or 62 5 µm core diameter cable should be used For distances up to 125 meters 62 5 µm can be used 50 µm cable allows distances ...

Page 23: ...mation Machine __________________________________________ OS Name __________________________________________ OS Version __________________________________________ Card Type __________________________________________ Card Serial __________________________________________ Software Part __________________________________________ Software S N __________________________________________ Problem Reproduc...

Page 24: ...INSTALLATION This page intentionally left blank Copyright 2006 3 4 FibreXtreme Hardware Reference Manual ...

Page 25: ... adequately addressed by the host interface CAUTION FibreXtreme Serial FPDP Protocol Analyzer Errata When a FibreXtreme Serial FPDP Protocol Analyzer is receiving data from a Serial FPDP device that uses a Xilinx RocketIO multi gigabit transceiver MGT for 8B 10B encoding the analyzer erroneously reports 1 CRC errors where no CRC error actually exists 2 A data throughput that is one half of the act...

Page 26: ... to how full the receive FIFO is this is not the SUSPEND from an FPDP port All FPDP signals with the exclusion of SYNC are passed around the receive FIFO and are not synchronized with the data stream For PCI variations of this card the FPDP signals can be read from a register once they are received from the link 4 2 2 Transmit Operation The transmit operation first has to collect data in the trans...

Page 27: ...ugh If it is not configured to receive the data it simply passes the data through the Retransmit FIFO without modifying the suspend request Serial FPDP supports the DIR NRDY PIO1 and PIO2 FPDP signals These signals do not propagate through the Transmit FIFO or the Receive FIFO and thus cannot be directly associated with the corresponding data To guarantee a pulse on these signals is propagated to ...

Page 28: ...nfiguration Options There are many different configuration options available which affect the operation of the SL240 card Most of these options are configured in the Link Control register described in Appendix B 4 4 1 Flow Control Flow control allows a Serial FPDP receiver to throttle the data stream from a Serial FPDP transmitter If this option is turned off the card will continue to send data ev...

Page 29: ...r third party devices Both nodes on the link or all nodes in a loop configuration should be set to a common CRC mode or the resulting mismatch will cause data errors and or link errors 4 4 5 Stop on Link Error or SYNC There are two DMA stop conditions available to the user stop on link error and stop on SYNC The stop on link error stops the DMA engine from removing data from the receive FIFO when ...

Page 30: ...OPERATION This page intentionally left blank Copyright 2006 4 6 FibreXtreme Hardware Reference Manual ...

Page 31: ...LE OF CONTENTS A 1 Specifications A 1 A 1 1 66 MHz CCPMC Specifications A 1 A 2 Ruggedized PMC Environmental Specifications A 1 A 2 1 Rugged Level 2 A 1 A 3 Media Interface Specifications A 2 A 3 1 SL240 Fibre Optic Media Interface Specifications A 2 ...

Page 32: ......

Page 33: ... Power 7 2 W peek at 3 3 Volts 12 W peek at 5 Volts Electrical Requirements SL240 2 18 Amps peek at 3 3 Volts 024 Amps peek at 5 Volts Operating Temperature Range 40 to 85 C Storage Temperature 40 to 85 C A 2 Ruggedized PMC Environmental Specifications A 2 1 Rugged Level 2 Temperature Range Operating 40 to 85 C Storage 40 to 85 C Humidity Range Operating 0 to 95 noncondensing Storage 0 to 95 nonco...

Page 34: ...nformation on the coating can be found at the HumiSeal website http www humiseal com A 3 Media Interface Specifications A 3 1 SL240 Fibre Optic Media Interface Specifications Connector Duplex LC 850 nm Media 50 µm or 62 5 µm multimode fiber Maximum Fiber Length 150 m with 50 µm fiber 125 m with 62 5 µm fiber Transmit Wavelength 830 to 860 nm Transmit Power 10 to 4 dBm Receive Wavelength 770 to 860...

Page 35: ...R Offset 0x00 B 3 B 4 3 Board CSR BRD_CSR Offset 0x04 B 4 B 4 4 Link Control LINK_CTL Offset 0x08 B 5 B 4 5 Link Status LINK_STAT Offset 0x0C B 8 B 4 6 FPDP Flags FPDP_FLGS Offset 0x10 B 9 B 4 7 Receive FIFO Threshold Offset 0x14 B 10 B 4 8 Laser Transmitter Control Offset 0x18 B 10 B 4 9 Transaction Channel 0 Send Channel B 11 B 4 10 Transaction Channel 1 Receive Channel B 14 TABLES Table 1 1 SL2...

Page 36: ......

Page 37: ...isms for accessing these are platform specific and therefore outside the scope of this document though the contents are detailed here B 3 PCI Configuration registers The PCI SL240 card contains a standard PCI configuration space header with the device ID of 0x4640 and the vendor ID of 0x1387 There are also two base addresses initialized for the card the first is a 256 byte space representing the r...

Page 38: ... Length 0 Transaction CSR 0 0x38 Reserved Reserved 0x40 Reserved Chain PCI Address 0 0x48 Next Chain Entry 0 Chain Length Flags 0 0x50 Reserved Queue Address 1 0x58 Reserved Queue Control 1 0x60 Transaction Length 1 Transaction CSR 1 0x68 Reserved Reserved 0x70 Reserved Chain PCI Address 1 0x78 Next Chain Entry 1 Chain Length Flags 1 0x80 0x88 0x90 0x98 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0...

Page 39: ...indicates not active Write 1 to clear R WOC 0 6 Threshold Interrupt A 1 indicates active a 0 indicates not active Write 1 to clear R WOC 0 15 to 7 Reserved None 0 16 Enable Transaction Channel 0 Interrupt Set to 1 to enable interrupts set to 0 to disable R W 0 17 Enable Transaction Channel 1 Interrupt Set to 1 to enable interrupts set to 0 to disable R W 0 18 Enable DMA Chain 0 Interrupt Set to 1 ...

Page 40: ...V PCI signaling A 0 indicates the SL240 card uses 5 V PCI signaling R See desc 15 SL240 A 1 indicates this is an SL240 board R See desc 23 to 16 Extended Revision ID These bits are used to identify intermediate or special firmware revisions Note 1 R See desc 24 Big Endian Set to 1 to swap the control registers Set to 0 for Little Endian R W 0 25 64 bit transaction disable Set to 1 to disable 64 bi...

Page 41: ...ransmitting when the link is down Set to 0 to stop transmission when the link goes down or the remote end is sending a STOP ordered set back NOTE In almost every application flow control should be enabled Even if the application must sustain maximum link throughput it is better to drop the data at the sending source should the system experience a temporary overload condition In some rare cases flo...

Page 42: ...the LWRAP bit R W 0 10 EWRAP This signal controls loopback operation of the user interface s data stream A 1 indicates the outgoing data stream is electronically wrapped into the incoming data stream at the serializer deserializer A 0 indicates non wrapped data flow to and from the link interface This is typically used for testing purposes R W 0 11 LWRAP This signal controls the loopback operation...

Page 43: ...t be used in the majority of applications Resetting the Transmit FIFO or Receive FIFO independently from the SL240 FPGA logic can cause undesirable effects because each 32 bit Serial FPDP data word occupies two entries in the respective FIFO and the link and host are independently filling and draining these FIFOs Applying the FIFO resets without applying special precaution can result in a misalign...

Page 44: ...he card has corrected a synchronization error on the incoming data stream A 0 indicates the card has not corrected a synchronization error on the incoming data stream This bit is cleared through Reset SR in LINK_CTL R 0 11 Checksum Error A 1 indicates the card has detected a checksum error on the incoming data stream A 0 indicates the card has not detected a checksum error on the incoming data str...

Page 45: ...ote transmitter This bit is read only and will be dynamically changing R 0 15 FIFO Overflow Indicates that the Remote Transmitter FIFO Overflow bit was set in the received Status End of Frame primitive EOFa or EOFn Fibre Channel ordered sets This indicates that the remote node detected an overflow condition in its transmit FIFO This bit is read only and will be dynamically changing R 0 16 Latched ...

Page 46: ... Interrupt Threshold Selects one of the following levels of the Receive FIFO to interrupt on 00 Interrupt threshold set to Receive FIFO Not Empty 01 Interrupt threshold set to Receive FIFO Full 10 Interrupt threshold set to Receive FIFO Full 11 Interrupt threshold set to Receive FIFO Full R W 0 B 4 8 Laser Transmitter Control Offset 0x18 Field Description Access Reset Value 25 to 0 Reserved None 0...

Page 47: ...0 24 Enable Queue A 1 enables the queue to fetch transaction entries Setting this bit to 0 pauses the transaction queue R W 0 25 Reset Queue Write 1 to set the consumer and producer indices to 0 Writing 0 has no effect W 0 26 Abort Queue Write 1 to this bit to abort the current transaction pending on the transaction controller Writing 0 has no effect W 0 27 Reserved None 0 28 Stop on link error Se...

Page 48: ... the transaction entry in memory on Link Error Set to 0 not to abort R W 0 7 to 6 Reserved None 0 8 Send a SYNC without DVALID after this transaction is finished Set to 1 to send set to 0 not to send Do not set both bits 8 and 9 R W 0 9 Send a SYNC with DVALID after this transaction is finished Set to 1 to send set to 0 not to send Do not set both bits 8 and 9 R W 0 31 to 10 Reserved None 0 Send T...

Page 49: ...erved None 0 29 Interrupt Write 1 to interrupt on transfer complete Write 0 otherwise R W 0 30 Go Set to 1 to start this transaction 0 to stop it If it is a chained transaction the first action is to fetch the chain entry R W 0 31 Done A 1 indicates this channel is currently idle A 0 indicates a DMA is in progress R 0 Send Next Chain Entry CNEXT0 Offset 0x4C Field Description Access Reset Value 3 ...

Page 50: ...eue to fetch transaction entries Setting this bit to 0 pauses the transaction queue R W 0 25 Reset Queue Write 1 to set the consumer and producer indices to 0 Writing 0 has no effect W 0 26 Abort Queue Write 1 to this bit to abort the current transaction pending on the transaction controller Writing 0 has no effect W 0 27 Stop on SYNC Set to 1 to disable the controller on SYNC received Set to 0 fo...

Page 51: ...C Set to 0 not to abort R W 0 5 Abort Writeback on Link Error Set to 1 to abort the current transaction and write the status back to the transaction entry in memory on Link Error Set to 0 not to abort R W 0 9 to 6 Reserved None 0 10 Received SYNC without DVALID R 0 11 Received SYNC with DVALID Convert SYNC must be enabled in the Link Control register for this bit to be valid R 0 31 to 12 Reserved ...

Page 52: ... Reserved None 0 29 Interrupt Write 1 to interrupt on transfer complete Write 0 otherwise R W 0 30 Go A 1 starts this transaction A 0 stops it If it is a chained transaction the first action is to fetch the chain entry R W 0 31 Done A 1 indicates this channel is currently idle A 0 indicates a DMA is in progress R 0 Receive Next Chain Entry CNEXT0 Offset 0x7C Field Description Access Reset Value 3 ...

Page 53: ...Sets Used C 1 C 3 Frames C 3 C 3 1 Link Bandwidth C 4 C 3 2 FPDP Signal Sample Rate C 4 C 4 Data Transmission and Flow Control C 5 FIGURES Figure C 1 VITA 17 1 Framing Protocol C 3 TABLES Table C 1 Ordered Set Mapping C 2 Table C 2 Maximum Sustained Throughput C 4 Table C 3 Sampling Frequencies C 4 ...

Page 54: ......

Page 55: ...8B 10B protocol to be ordered sets which denote special control information for Fibre Channel These same ordered sets are used in VITA 17 1 but are assigned different meaning There are eighteen ordered sets used by SL240 to denote different information Twelve of these ordered sets are used to embed five bits of data eight start of frame SOF sets are used to embed three bits at the start of a frame...

Page 56: ...e PIO1 1 PIO2 1 DIR 1 EOFt SEOF Status EOF FIFO Overflow 0 NRDY 0 EOFdt SEOF Status EOF FIFO Overflow 0 NRDY 1 EOFa SEOF Status EOF FIFO Overflow 1 NRDY 0 EOFn SEOF Status EOF FIFO Overflow 1 NRDY 1 EOFni MEOF Mark EOF EOF for a SYNC frame EOFdti FEOF Frame EOF EOF for a normal data frame R_RDY SWDV SYNC with DATA Valid Says that the next frame will be a SYNC with DATA frame NOS STOP Tells the rem...

Page 57: ...ted and the proper SYNC frame SYNC with data or SYNC without data is sent Figure C 1 shows the four types of frames and the ordered set placement within those frames IDLE SOF CRC GO STOP SEOF IDLE Fiber Frame IDLE SOF CRC GO STOP SEOF 1 To 512 4 Byte Data Words Maximum 2048 Bytes Data Fiber Frame SWDV SOF CRC GO STOP SEOF 1 Data Word 4 Bytes No More No Less Sync With Data Fiber Frame IDLE SOF CRC ...

Page 58: ...Mode Master bit 1 SL240 247 10 MB s 247 58 MB s 245 68 MB s 246 15 MB s NOTE The Copy Master Mode is located in the Link Control register C 3 2 FPDP Signal Sample Rate The states of the FPDP signals PIO1 PIO2 DIR and NRDY are transmitted across the link at varying rates The worst case rate at which these signals are sampled is for CRC checked filled data frames and the Copy Mode Master bit set In ...

Page 59: ...l the signal changes Curtiss Wright Controls SL240 boards use the same protocol when transmitting from either end to allow the link to operate bi directionally Since these data streams are independent the maximum throughput on the link would be 494 MB s for SL240 The receiver should transmit the STOP signal when it has space for the data contained in 20 km of fiber or less left Assuming 5 µs km fo...

Page 60: ...SL240 PROTOCOL This page intentionally left blank Copyright 2006 C 6 FibreXtreme Hardware Reference Manual ...

Page 61: ...N APPENDIX D ORDERING INFORMATION TABLE OF CONTENTS D 1 Overview D 2 Ordering Information D 1 D 2 1 Short Wavelength Multimode Fiber Optic Cables D 1 TABLES Table D 1 LC to LC D 1 Table D 2 LC to ST D 1 Table D 3 SC to LC D 1 ...

Page 62: ......

Page 63: ...M2LC2001 00 20 meters LC LC FHAC M1LC3001 00 FHAC M2LC3001 00 30 meters LC LC FHAC M1LCxxxx 00 FHAC M2LCxxxx 00 Custom LC LC Table D 2 LC to ST Simplex Part Number Duplex Part Number Length Cable End 1 Cable End 2 FHAC M1LCST03 00 FHAC M2LCST03 00 3 meters LC ST FHAC M1LCST05 00 FHAC M2LCST05 00 5 meters LC ST FHAC M1LCST10 00 FHAC M2LCST10 00 10 meters LC ST FHAC M1LCST20 00 FHAC M2LCST20 00 20 m...

Page 64: ...ORDERING INFORMATION This page intentionally left blank Copyright 2006 D 2 FibreXtreme Hardware Reference Manual ...

Page 65: ...1 GLOSSARY GLOSSARY ...

Page 66: ......

Page 67: ... the host CPU for other tasks FibreXpress board becomes a master for the bus FC Fibre Channel FC PH Fibre Channel Physical interface Fibre Channel Physical standard consisting of the three lower levels FC 0 FC 1 and FC 2 Fibre Channel Fibre Channel FC is a serial data transfer interface technology operating at speeds up to 1 Gbps It is defined as an open standard by ANSI It operates over copper an...

Page 68: ...us and change the configuration of the driver multicast A single transmission is sent to multiple destination N_ports a one to many transmission Multicasting provides a way for one host to send packets to a selective group of hosts N_Port Node Port A Fibre Channel defined entity at the node end of a link that connects to the fabric via an F Port network Connects a group of nodes providing the prot...

Page 69: ...nodes Non blocking port A physical element through which information passes It is an electrical or optical interface with a pair of wires or fibers one each for incoming and outgoing data SFF Small Form Factor Based on SFF MSA SFP Small Form Factor Pluggable based on MultiSource Agreement MSA September 14 2000 FO Transceiver Industry topology Refers to the order of information flow due to logical ...

Page 70: ...GLOSSARY This page intentionally left blank Copyright 2006 GLOSSARY 4 FibreXtreme Hardware Reference Manual ...

Page 71: ...1 INDEX INDEX ...

Page 72: ......

Page 73: ... 2 3 2 A 2 simplex LC 3 2 connectors fiber optic 3 2 control registers 4 5 copy master C 4 copy master mode B 6 C 4 copy mode master C 4 CRC 4 3 4 5 B 5 C 4 D data stream B 6 B 8 C 1 data frame 4 2 C 2 data frames C 4 data rate raw C 1 data storage elements 2 9 data stream 4 2 4 3 4 4 data swapping B 13 B 16 data synchronization 2 2 4 4 data throughput rate 2 5 data transfer maximum 2 7 segment 4 ...

Page 74: ...nterrupt threshold B 3 B 10 interrupt enable B 12 B 15 interrupt threshold B 10 L laser manual shutdown B 10 short wavelength 2 2 3 2 D 2 latency reduce 4 2 LED status 2 2 link duplex fiber optic 4 4 error 4 5 point to point C 5 throughput 4 5 link error B 11 B 12 B 14 B 15 link failure 2 2 link interface 2 1 3 1 B 6 link protocol 4 2 4 3 link stability 2 2 link throughput maximum B 5 link transmi...

Page 75: ...nsions A 1 PIO 4 2 4 5 B 4 PIO1 4 2 PIO2 4 2 PMC installation 3 1 port fault isolation 2 4 FPDP 4 2 JTAG B 4 RS 232 2 4 portability 4 1 ports non blocking 2 4 power dissipation A 1 transmit A 2 power usage A 1 programming 1 1 2 2 B 1 R receive interface 4 3 receive wavelength A 2 receiver node C 5 record playback 4 5 record playback systems 2 9 register 4 2 4 3 configuration B 1 control B 1 link c...

Page 76: ...onization process 4 4 system performance 4 4 T temperature range A 1 threshold interrupt 4 5 threshold register B 10 throughput 2 2 4 2 4 4 C 4 end to end 2 2 enhanced 2 2 high 2 5 maximum C 5 maximum sustained C 4 optimal C 1 usable C 1 topology 2 7 3 2 B 6 chained 2 7 2 8 multiple master loop 2 7 multiple master ring 2 10 point to point 2 7 B 6 B 7 single master loop 2 7 single master ring 2 9 t...

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