Curtiss-Wright FHA5-XE1MWB04-00, User Manual

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10-6
SL240 XMC User Guide
APPENDIX D
Copyright 2017
10.3 Parallel FPDP Theory of Operation
10.3.1 Clock Signals
A single FPDP-TM generates a free-running clock. This clock frequency determines the
maximum transfer rate on the bus. FPDP provides both a PECL (Positive Emitter Coupled
Logic) and TTL strobe on the bus, with the PECL clock used for higher frequency (> 20 MHz)
transfers. If designing to the CMC card, only an LVTTL clock is generated by the card’s FPDP
transmitter port, since it is driving to a PCB instead of a long ribbon cable.
An FPDP receiver card (FPDP-R or FPDP-RM) accepts the PECL or TTL clock generated by
the transmitter and uses it as the word clock for the data transfers. This clock is generally in the
range of 0 to 40 MHz on standard FPDP busses, though the FPDP specification does not state a
hard maximum frequency at which the bus may be run. The CMC card has a LVTTL clock input
that it uses for the word clock.
10.3.2 Data Framing
The FPDP specification does not allow for the transmission of address information. However,
many systems have data coming from several cards or channels. The way to identify data from
each channel is through framing. A synchronization pulse signal, /SYNC, was defined for framing
purposes. The frame size is defined as the number of data items in the frame. Unframed data
may also be transmitted onto the FPDP bus. The four data frame types defined by the FPDP
specification are listed and described below.
·
Unframed data
·
Single frame data
·
Fixed size repeating frame data
·
Dynamic size repeating frame data
UNFRAMED DATA
·
Used when the source and the organization of the data is not important.
·
Used when the FPDP receivers do not need to be synchronized to the data stream.
·
/SYNC is not required.
When unframed data is transmitted onto the FPDP bus, no synchronization is required.
Thus, the FPDP-TM must not generate /SYNC, and the FPDP-RM and FPDP-R
devices must not require a /SYNC pulse in order to correctly receive data.
SINGLE FRAME DATA
·
Synchronization must occur prior to data to which it applies.
·
Synchronization occurs between data blocks.
·
/SYNC must be asserted before /DVALID is asserted.
·
Synchronization occurs infrequently, perhaps only once.
When single frame data is transmitted onto the FPDP bus, the FPDP-TM must assert
a /SYNC pulse before valid data starts being transmitted. Valid data is transmitted
when the data valid signal /DVALID is asserted. Thus, a /SYNC pulse must be
asserted before /DVALID is asserted when transmitting single frame data. After a /
SYNC pulse is asserted, the FPDP-RM and FPDP-R devices should not accept data
until the first STROBE period after /DVALID is asserted. The /SYNC pulse does not
have to be asserted again until before the start of the next data transmission.