Curtiss-Wright Compact CHAMP-AV IV User Manual Download Page 70

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814256 V

ERSION

2 F

EBRUARY

2006

A-1

ONNECTOR

SSIGNMENTS

HIS

PPENDIX

...

This appendix provides the interface pinout information for each of the connectors on the
Compact CHAMP-AV IV. The following connectors are described:

• “J1 Connector Pin Assignments” on page A-2

• “J2 Connector Pin Assignments” on page A-4

• “J3 Connector Pin Assignments” on page A-6

• “J4 Connector Pin Assignments” on page A-8

• “J5 Connector Pin Assignments” on page A-10

• “PMC Connectors” on page A-12

– “J11 Connector” on page A-13

– “J12 Connector” on page A-15

– “J13 Connector” on page A-17

– “J14 Connector” on page A-19

– “J21 Connector” on page A-21

– “J22 Connector” on page A-23

– “J23 Connector” on page A-25

– “J24 Connector” on page A-27

– “PMC to cPCI Connector Mapping for Differential Signaling” on page A-29

– “PMC to cPCI Connector Mapping for Single-Ended Signaling” on page A-30

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Summary of Contents for Compact CHAMP-AV IV

Page 1: ...utilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of their respective owners...

Page 2: ... Embedded Computing 333 Palladium Drive Ottawa Ontario Canada K2V 1A6 613 599 9199 COMPACT CHAMP AV IV QUAD POWERPCTM SCP 424 USER S MANUAL 814256 2 February 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...will be construed as an acceptance of the foregoing condition Copyright 2006 Curtiss Wright Controls Inc All rights reserved TRADEMARKS Acrobat is a trademark of Adobe Systems Incorporated Altivec is a trademark of Motorola Inc Ethernet is a trademark of Xerox Corporation PowerPC is a trademark of International Business Machines Corporation UNIX is a registered trademark in the U S and other count...

Page 4: ... 26 Operating System Software 1 26 Optimized DSP Libraries 1 27 Software Development Tools 1 27 2 Pre Installation Tasks 2 1 Unpacking the Card 2 2 Checking Hardware Requirements 2 2 Chassis Requirements 2 2 Power Requirements 2 2 Flash Configuration Parameters 2 4 PMC PMC X Module Installation Requirements 2 4 Configuring Switches 2 8 3 Hardware Installation 3 1 Installation Prerequisites 3 2 Ins...

Page 5: ...ector Pin Assignments A 4 Electrical Characteristics of J2 Signals A 5 J3 Connector Pin Assignments A 6 Electrical Characteristics of J3 Signals A 7 J4 Connector Pin Assignments A 8 Electrical Characteristics of J4 Signals A 9 J5 Connector Pin Assignments A 10 Electrical Characteristics of J5 Signals A 11 PMC Connectors A 12 J11 Connector A 13 J12 Connector A 15 J13 Connector A 17 J14 Connector A ...

Page 6: ...Asynchronous Mode 1 17 Figure 1 8 Compact CHAMP AV IV Board Layout 1 21 Figure 1 9 Bottom View of Compact CHAMP AV IV PWB 1 22 Figure 2 1 Position of 5V and 3 3V Keying Holes on a PMC Board 2 5 Figure 2 2 Configuration Switch Locations 2 9 Figure 4 1 Data Access Directions for Processor Nodes 4 5 Figure 4 2 Data Access Directions for PMCs 4 6 Figure A 1 J1 Connector A 2 Figure A 2 J2 Connector A 4...

Page 7: ...COMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING VI 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 8: ...ector Description A 3 Table A 3 J2 Connector Pin Assignments A 5 Table A 4 J2 Connector Description A 5 Table A 5 J3 Connector Pin Assignments A 7 Table A 6 J3 Connector Description A 7 Table A 7 J4 Connector Pin Assignments A 9 Table A 8 J4 Connector Description A 9 Table A 9 J5 Connector Pin Assignments A 11 Table A 10 J5 Connector Description A 11 Table A 11 J11 Connector Description Pn1 Jn1 64...

Page 9: ...OMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING VIII 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 10: ...on instructions programming interface detailed connector pinout info Compact CHAMP AV IV Hardware Documentation Contents information describing the exact hardware configuration of your Compact CHAMP AV IV board Compact CHAMP AV IV Product Release Notes 8xxxxx CHAMPtools Software Documentation CHAMPtools Software User s Manual 811489 Contents Software architecture overview BootMon description Board...

Page 11: ...eration of the version 1 2 WIND POWER ICE and visionPROBE II emulators is provided in the following Wind River Systems publications WIND POWER ICE for WIND POWER IDE User s Guide part DOC 15149 NN 00 WIND POWER IDE Getting Started part DOC 15146 ZD 00 WIND POWER IDE Release Notes visionPROBE II for WIND POWER IDE User s Guide part DOC 15145 ND 00 CONVENTIONS USED IN THIS MANUAL This document and t...

Page 12: ... File names are set in italics Copy the file named bootA exe Directory Names Directory names show the full directory path The last directory in the path does not have a trailing slash following it Go to the c windows temp backup directory Monitor Displays Prompts and other text appearing on monitors is set in bold monospace type BootMon Firmware Code Firmware code and any informtion you need to ty...

Page 13: ...n a subject being discussed is addressed in depth by another more authoritative document Cross references are also used for document chapters and sections The warning icon indicates procedures in the manual that if not carried out or if carried out incorrectly could cause physical injury electrical damage to equipment or a non recoverable corruption of data Warnings include instructions for preven...

Page 14: ...2 2004 MV64460 MV64461 MV64462 System Controller for PowerPC Processors Part 2 of 2 User Manual Doc Number MV S101286 00 Revision B Marvell July 22 2004 Double Data Rate DDR SDRAM Spec JEDEC Standard No 79 Release 2 Feb 2002 Stub Series Terminated Logic for 2 5V SSTL_2 JESD8 9A Dec 2000 MPC8540 Integrated Processor Hardware Specification Rev 3 1 12 2004 MPC8540 PowerQUICC III Integrated Host Proce...

Page 15: ...OMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING XIV 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 16: ... Architecture on page 1 5 Processor Nodes on page 1 5 Double Data Rate SDRAM on page 1 6 Flash Memory on page 1 7 High Speed SRAM on page 1 7 PMC X Sites on page 1 7 PCI Local Bus on page 1 8 On Board Interrupt and Control cOBIC on page 1 8 Serial Ports on page 1 17 Ethernet Interfaces on page 1 18 Power on page 1 18 Reset on page 1 19 Timers on page 1 19 Temperature Voltage Sensors on page 1 19 A...

Page 17: ...MP AV IV also has a powerful fifth processor the Freescale MPC8540 PowerQUICC III The Compact CHAMP AV IV is particularly well suited to large multi slot systems This is by virtue of its four 800 MB sec peak PCI buses and its five Gigabit Ethernet connections one per processor which together provide very high I O throughput and switching bandwidth This together with its four altivec enabled 7447A ...

Page 18: ... Control cOBIC Compact PCI User I O MPC7447 A 7448 PowerPC A MV64460 Bridge A Local DDR SDRAM 256 MB 512 MB MPC7447 A 7448 PowerPC D MV64460 Bridge D Local DDR SDRAM 256 MB 512 MB MV64460 Bridge C MV64460 Bridge B MPC7447 A 7448 PowerPC C MPC7447 A 7448 PowerPC B Local DDR SDRAM 256 MB 512 MB Local DDR SDRAM 256 MB 512 MB PMC1 PMC2 MPC8540 FLASH 32 128 MB 64 bit up to 99 MHz PCI X Bus 64 bit up to...

Page 19: ...l PowerPC 8540 at 500 800 MHz for control functions 256 or 512 Mbytes DDR SDRAM QuadFlow architecture with up to 3 2 GB s peak on board throughput Five Gigabit Ethernet GbE ports one per processor PICMG 2 16 compliance Support for two 64 bit 100 MHz PCI X mezzanine modules PMC X Two EIA 232 serial ports Support for switch fabric PMC modules with differential routing to backplane VxWorks Board Supp...

Page 20: ...r with 1 Mbyte 7448 512 Kbytes 7447A of internal L2 cache and its own dedicated bank of DDR 266 SDRAM Each processor node incorporates a Marvell MV64460 Discovery III bridge which acts as a non blocking crossbar interface between the MPC7448 7447A processor the DDR SDRAM two 64 bit 100 MHz PCI X buses and Gigabit Ethernet See Figure 1 2 for additional details FIGURE 1 2 Processor Node Block Diagra...

Page 21: ...ery III bridge provides four DMA controller engines which are capable of transfering data between any of the bridges interfaces The DMA capability is particularly useful for managing transfers between processor node memory banks and transfers to and from PMC devices In addition the Discovery III bridge provides two XOR DMA controller engines that can read from up to eight sources perform bitwise X...

Page 22: ...SITES The Compact CHAMP AV IV is equipped with two mezzanine sites compatible with the PCI PMC and PCI X PMC X standards The PMC X interfaces support 64 bit PCI X100 transfers 100 MHz PCI X with a resulting peak rate of 800 MB s The board is backward compatible with PCI X66 66 MHz PCI X PCI 66 66 MHz conventional PCI and PCI 33 33 MHz conventional PCI The interfaces are mapped to all five processo...

Page 23: ...PCI X mode at 100 MHz 64 bit However the speed of PCI PCI X buses between Nodes B and C and between Nodes A and D will depend upon the PMC X PMC that is installed on those buses A 33 or 66 MHz PMC will drop the speed of the bus on which it is installed to PCI33 or PCI66 PCI mode at 33 or 66 MHz respectively A signalling voltage of 5 volts VIO will also drop the speed of the PCI bus to PCI33 ON BOA...

Page 24: ...g An External Interrupt Module Twenty Four external interrupts supplied to the cOBIC Interrupt detection and steering Interrupt masking An Inter Processor Module Mailbox Interrupts supported by five FIFOs one per processor Only the processor that owns a FIFO can read it while all processors can write it Dedicated inter processor interrupts Sixteen semaphore registers Five Watchdog timers one per p...

Page 25: ... to be less then optimum The Compact CHAMP AV IV allows the hardware to adapt to the needs of the software All of the internal and external interrupt sources PMC modules GPIO PCI etc are routed into a software configurable multiplexer that allows any processor to receive interrupts from any device This feature speeds interrupt response time by routing the interrupt directly to the intended process...

Page 26: ...terrupt Status Read Write to clear Interrupt Mask Read and Write Interrupt Pending Read DVX_INT_ 0 is the logical OR of ProcX_IP1 bits DVX_INT_ 1 is generated by ORing the bits of ProcX_IP2 and ProcX_IP3 OR CPCI_GPIO 2 1 DVX_INT_ PMC1_INT_ A D PMC2_INT_ A D DVA_PCI_INT_ 1 0 DVB_PCI_INT_ 1 0 DVE_PCI_INT_ 1 0 DVC_PCI_INT_ 1 0 DVD_PCI_INT_ 1 0 TEMP_VOLT 1 0 2 Interrupt Mask Register INT_88E1111 P 3 0...

Page 27: ...f five FIFOs for support of mailbox interrupts five inter processor interrupt registers sixteen semaphore registers five watchdog timers and a multi board synchronous timer These features are described below Mailbox Interrupts The cOBIC provides mailbox interrupts whereby a processor can interrupt another processor and deliver a 16 bit value Each processor has a 16 bit 32 deep FIFO Any processor c...

Page 28: ...or A with a status value reflecting INT3 asserted in the Inter Processor Interrupt Status register The user must write a one to this bit to clear the interrupt TABLE 1 3 Inter Processor Interrupt Generation Register Processor Identification Bits Interrupt Identification Bits 7 6 5 4 3 2 1 0 Not Used Not Used Processor Identification Bits 5 3 Definition 000 Reserved 001 Interrupt Processor A 010 In...

Page 29: ...imately 970 ns Time out periods from 1 µs to 16 seconds can be programmed Initialization software can select whether a watchdog exception event causes an interrupt a local processor reset or a card reset The watchdog can be locked so that once enabled to cause a reset the watchdog cannot be disabled The watchdog timer can be used in two ways As a standard watchdog timer a single time period is pro...

Page 30: ...revious kick or from the original start When a fault occurs you want the processor associated with that watchdog timer to be reset To set up this scenario first clear the WDT_EN bit in the Watchdog Control Register This disables the watchdog timer Then set the WDT_RST_EN bit in the Watchdog Control Register to allow a reset of the processor if a fault occurs Then write 0x0000_3053 to the Watchdog ...

Page 31: ...the Compact CHAMP AV IV surface mount LEDs can be controlled by any of the processors writing to the Global LED register Further each of the processors has a processor LED register that controls the green processor status LED and two of the surface mount status LEDs See Figure 1 6 on page 1 16 for additional information There is an additional red LED on the front panel used to indicate a failure d...

Page 32: ...lemented in the 8540 On board EIA 232 transceivers are used to convert the electrical signals between EIA 232 and LVTTL levels Nodes A and E Serial Port 0 EIA 232 Asynchronous Mode Figure 1 7 illustrates the signal names and direction input or output associated with Serial Port 0 on Nodes A and E FIGURE 1 7 Nodes A and E Serial Port 0 EIA 232 Asynchronous Mode TABLE 1 5 Serial Port Summary PORT SI...

Page 33: ...00Base T polarity reversal does not matter Each Discovery III uses an RGMII Reduced Gigabit Media Independent Interface to transfer data between itself and the Quad PHY Processor E MPC8540 uses its internal Gigabit Ethernet MAC interface The 8540 Ethernet controller also implements a number of features that are designed to minimize processor loading due to Ethernet traffic These include dedicated ...

Page 34: ... 1 22 In revision A of the Compact AV IV baseboard the sensors are connected to Node A of the Discovery III bridge In revision B and later of the Compact AV IV baseboard the sensors are connected to both Node A of the Discovery III bridge as well as to the MPC8540 Each sensor IC is capable of measuring three temperatures one local temperature and two remote temperatures The local temperature is th...

Page 35: ...or has twelve programmable ALERT thresholds consisting of a high and low threshold for each temperature sensor and each voltage sensor Each sensor has an open drain over temperature OVERT output The OVERT output from both sensors are wire ored together and connected to the on board power control circuitry If either sensor s OVERT output is asserted the on board power control circuitry will turn of...

Page 36: ...134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C1282 D1 D2 D3 D4 D5 DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9 DS10 DS11 DS12 DS13 DS14 DS15 DS16 DS17 DS18 DS19 DS20 DS21 DS22 DS23 DS24 J1 J2 J3 J4 J5 J11 J12 J13 J14 J21 J22 J23 J24 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 Q1 Q2 Q3 Q4 Q5 Q6 Q7 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R20 R21 R22 R23 R24 R25 R26 R27 R2...

Page 37: ...18 Q219 R1388 R1390 TP200 TP201 TP202 TP203 TP204 TP205 TP207 TP208 TP209 TP210 TP211 TP212 TP213 TP214 TP215 TP216 TP217 TP218 TP219 TP224 TP225 TP226 TP227 TP228 TP229 TP230 TP231 TP234 TP235 TP236 TP237 TP238 TP241 TP242 TP243 TP244 TP245 TP246 TP247 TP248 TP249 TP251 TP253 U200 U201 U202 U203 U204 U205 U206 U207 U208 U209 U210 U211 U212 U213 U214 U215 U216 U217 U218 U219 U220 U221 U222 U223 U2...

Page 38: ...modules that may be installed on the basecard PWB If there are no PMC modules mounted the openings are filled with bezels Reset Pushbutton This button can be used to initiate a card reset Processor Status LEDs A B C D E Each of the processors has a processor LED register that controls the green processor status LEDs seen opposite and two of the surface mount status LEDs on the PWB F LED The F LED ...

Page 39: ...C module site 2 I O signals are accessible via the basecard P2 con nector rows A and C J3 95 pin 5 x 19 2mm connector PMC Site 2 I O signals Gigabit Ethernet interfaces forn processors A and B J4 125 pin 5 x 25 2mm connector Gigabit Ethernet interfaces for processors C D and E GPIO signals PowerPC COP emulator interface signals J5 110 pin 5 x 22 2mm connector PMC Site 1 I O signals EIA 232 serial ...

Page 40: ...ERSION 2 FEBRUARY 2006 1 25 WEIGHT Table 1 9 lists the weight of the Compact CHAMP AV IV TABLE 1 9 Compact CHAMP AV IV Weight Card Type Weight Compact CHAMP AV IV est 1 3 lbs TBD Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 41: ... to develop with a variety of operating systems and development tools The following operating systems are supported on the Compact CHAMP AV IV A VxWorks Board Support Package BSP is available with support for the Tornado development environment The BSP supports the VxWorks Shared Memory Networking feature This allows the user to share a single network connection between multiple processors In deve...

Page 42: ...development Some of these utilities are listed below Board Support Library The Board Support Library contains C functions to access hardware features of the Compact CHAMP AV IV such as interrupts semaphores VME Flash read write Watchdog Timer Multiboard Synchronization Timer indicator LEDs etc The Board Support Library is self contained code that be can used with or without an operating system Sof...

Page 43: ...OMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING 1 28 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 44: ...on page 2 2 Checking Hardware Requirements on page 2 2 Chassis Requirements on page 2 2 Power Requirements on page 2 2 Flash Configuration Parameters on page 2 4 PMC PMC X Module Installation Requirements on page 2 4 Configuring Switches on page 2 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 45: ... a PCIMG 2 16 compliant card that is designed to be used in a PICMG 2 16 or standard cPCI backplane POWER REQUIREMENTS The Compact CHAMP AV IV requires 5 V and 3 3 V power supplies in order to operate Table 2 1 shows the power requirements for the Compact CHAMP AV IV Warning To avoid personal injury or damage to this Circuit Card Assembly disconnect the chassis from its power source before removin...

Page 46: ...ltages In order to ensure proper operation of the Compact CHAMP AV IV board the remote voltage sense lines for the 5V and 3 3V power must be connected from the power supplies to the voltage rails on the backplane Chassis units with built in power supplies furnished by most vendors should already have these lines connected However if the chassis is powered from a user supplied power source these li...

Page 47: ... 2001 June 14 2001 PCI X Auxiliary Standard for PMCs and Processor PMCs VITA39 2002 Draft 0 9a Sep tember 17 2002 PCI X Electrical and Mechanical Addendum to the PCI Local Bus Specifications PCI_SIG Rev 2 0 Nov 4 2002 PCI X Protocol Addendum to the PCI Local Bus Specification PCI SIG Rev 2 0 July 29 2002 PMC Module Voltage Types A PMC can be a 3 3V board uses 3 3V signaling a 5V board uses 5V sign...

Page 48: ...s as well as high speed differential PMCs PMC BUSMODE Signals On the Compact CHAMP AV IV the PMC BUSMODE 4 2 signals are hardwired and constantly drive the following values in accordance with the Common Mezzanine Card specification BUSMODE 4 2 0b001 This signals the PMC card that it is connected to a PMC site If the card is a PMC card it will drive a logic 0 on BUSMODE1 this signal has been rename...

Page 49: ...ected PCIXCAP PCIXCAP Jn1 pin 39 is a 3 level signal that is utilized to select between conventional PCI PCI 33 and PCI 66 PCI X 66 and PCI X 100 When the PMC grounds PCIXCAP conventional PCI mode is selected When the PMC connects PCIXCAP to ground through a 10 KOhm 5 resistor in parallel with a 0 01 µF 10 capacitor PCI X 66 MHz mode is selected When the PMC connects PCIXCAP to ground through a 0 ...

Page 50: ...your specific application and configuration Depending on the particular application and configuration various conditions can occur that could adversely affect and possibly damage the baseboard PMC s or chassis These conditions include but are not limited to excessive current drawn from the cPCI connectors excessive heating of baseboard and PMC components and reduction in board voltages that can ca...

Page 51: ...ing board switches and that you observe proper static control procedures when handling the card TABLE 2 5 Switch Definition Switch On Off Default S2 1 S2 3 User defined Switches are read by software on the Compact CHAMP AV IV and left up to the application On S2 4 Alternate FPGA PROM is used to program FPGA Main FPGA PROM is used program FPGA Off S3 1 User Defined readable by applications software...

Page 52: ...S6 DS7 DS8 DS9 DS10 DS11 DS12 DS13 DS14 DS15 DS16 DS17 DS18 DS19 DS20 DS21 DS22 DS23 DS24 J1 J2 J3 J4 J5 J11 J12 J13 J14 J21 J22 J23 J24 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 Q1 Q2 Q3 Q4 Q5 Q6 Q7 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 ...

Page 53: ...OMPACT CHAMP AV IV USER S MANUAL CURTISS WRIGHT CONTROLS EMBEDDED COMPUTING 2 10 814256 VERSION 2 FEBRUARY 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 54: ... on page 3 4 Detailed Installation Procedure on page 3 5 Insert the Basecard in the Chassis on page 3 5 Connect a Terminal on page 3 5 Connect Ethernet Port E on page 3 5 Cable Connections on page 3 5 Running the Boot Monitor on page 3 6 Initiate the Power Up Sequence on page 3 6 Display the Initial Screen Message on page 3 6 Configuring an Emulator for use with Compact CHAMP AV IV on page 3 8 Tro...

Page 55: ... you design your own RTM please contact CWCEC Technical Support first to make sure that your RTM design is compatible with the Compact CHAMP AV IV product UNPACK AND CONFIGURE THE CARD Ensure that you complete the pre installation tasks described in Chapter 2 of this manual and the pre installation tasks described in the User s Manuals for any PMC modules you need to install on the Compact CHAMP A...

Page 56: ...backplane J2 connector its I O signals are available on the backplane J3 connector CHOOSE A CPCI SLOT LOCATION The Compact CHAMP AV IV does not support cPCI System Slot capability therefore it cannot be installed in the System Slot usually marked off by different color card guides Additionally in a PICMG 2 16 chassis the Compact CHAMP AV IV is considered a Node board and must be installed in a PCI...

Page 57: ... on and then turn off to indicate a successful load of the cOBIC FPGA 7 Confirm two way RS 232 communication by entering help CR on the terminal emulator This command displays other commands supported by the boot monitor If the red LED flashes continuously but no information is displayed check the serial port configuration parameters and connection The flashing indicates the board has completed in...

Page 58: ... connector labelled ENET E on the RTM CABLE CONNECTIONS The following cables are required by the Compact CHAMP_AV IV board Cat 5 5E Shielded Twisted Pair Ethernet Cable with RJ 45 connectors on both ends DB 9 Female to DB 9 male serial cable These cables may be purchased through most electronics components retailers Tip Default serial communication parameters are 57 600 N 8 1 57600 baud no parity ...

Page 59: ... Inhibit Mode Recovery Mode and Flash Write Protect Mode INITIATE THE POWER UP SEQUENCE This section describes the normal power up behavior of the Compact CHAMP AV IV The Compact CHAMP AV IV Flash memory is managed by the A processor As a result processor A plays a unique role during board boot up After power on or board reset processor A loads and executes the Boot Monitor program stored in Flash...

Page 60: ...1066 MHz OBIC OBIC NG revision 0 c SIO Using default options Bridge configuring A Bridge configuring B Bridge configuring C Bridge configuring D Bridge configuring E PCI Bus 0 mode is 64 bit 66MHz PCI PCI Bus 1 mode is 64 bit 66MHz PCI PCI Bus 2 mode is 64 bit 66MHz PCI PCI Bus 3 mode is 64 bit 66MHz PCI PCI Scanning for devices delay 1000 mS PBIT cannot find pbit exe skipped Boot Inhibit jumper i...

Page 61: ... AV IV via the RTM 3 Select the processor to emulate via the rotary switch on the RTM 4 If the target processor is PPC A configure S3 3 and S3 4 to either of the Normal Boot Modes S3 3 and S3 4 both Off or both On Please note that if the board is in Boot Inhibit Mode or Recovery Mode processors B C and D are not automatically released from reset at power up or board reset since the startup code do...

Page 62: ...ction with the emulator 11 In order to execute user code on any of the processors load a program into the target using the emulator and then set the PC counter to the start address of the program To execute the code type go Warning Make sure that the signaling level on the emulator pod connected to the COP interface on the Compact CHAMP AV IV is set to 3 3V Failure to do so could cause damage to t...

Page 63: ...on and testing is complete It will then begin to blink regardless of the success or failure of the power on self tests indicating that the card is ready to accept input at the Boot Monitor prompt If the green Processor LEDs do not turn off it is possible the cOBIC FPGA has not loaded properly Power off the card then move switch S2 4 to the On position which selects the alternate SPROM see Table 2 ...

Page 64: ...MING INTERFACE IN THIS CHAPTER This chapter contains the following information Compact CHAMP AV IV Memory Map on page 4 2 Data Flow Directions on page 4 4 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 65: ...ge and FPGA port as starting at zero and extending through the first 512 MB of address space while the PCI address space for these assets never starts at zero PMC devices will view board resources using the PCI memory map where all processors start at a nonzero memory address Table 4 1 on page 4 3 shows the physical memory maps for all processors and for PMC initiated transfers No device may selec...

Page 66: ... MB PMC 2 PMC 2 PMC 2 PMC 2 PMC 2 PMC 2 C000_0000 CFFF_FFFF 256 MB illegal mem A mem A mem A mem A mem A D000_0000 D000_FFFF 64 KB illegal bridge A bridge A bridge A bridge A bridge A D010_0000 D010_FFFF 65 KB illegal OBIC A OBIC A OBIC A OBIC A OBIC A E000_0000 E7FF_FFFF 128 MB mem E mem E mem E mem E illegal mem E EC00_0000 EC0F_FFFF 64 KB E periph E periph E periph E periph illegal E periph EC1...

Page 67: ...ory mapped resources can access all other memory mapped resources on the Compact CHAMP AV IV board However because each PCI interface on a particular Discovery controller must be assigned unique PCI address ranges this is so that when the processor connected to the Discovery produces a PCI address that address will go out one and only one PCI interface a resource will be able to get to another res...

Page 68: ...Processor Nodes B A D C PMC1 E PMC2 C B A D PMC1 PMC2 E D C B A PMC2 E PMC1 A D C B PMC1 PMC2 E Resource Access Directions for Node A Resource Access Directions for Node B Resource Access Directions for Node C Resource Access Directions for Node D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 69: ...6 FIGURE 4 2 Data Access Directions for PMCs B A D C PMC1 E PMC2 Resource Access Directions for PMC2 Resource Access Directions for PMC1 Resource Access Directions for Processor E B A D C PMC1 E PMC2 E D C B A PMC2 PMC1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 70: ... Connector Pin Assignments on page A 8 J5 Connector Pin Assignments on page A 10 PMC Connectors on page A 12 J11 Connector on page A 13 J12 Connector on page A 15 J13 Connector on page A 17 J14 Connector on page A 19 J21 Connector on page A 21 J22 Connector on page A 23 J23 Connector on page A 25 J24 Connector on page A 27 PMC to cPCI Connector Mapping for Differential Signaling on page A 29 PMC t...

Page 71: ...ane i e E D C B A Figure A 1 shows the location of the contacts on the J1 connector FIGURE A 1 J1 Connector Table A 1 on page A 3 shows which signals are available from the J1 connector of the Compact CHAMP AV IV J1 J2 J3 J4 J5 A C D B F E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 J1 and J4 Connector Rear View Artisan Technology Group Quality Instrumentation Guaranteed 888 ...

Page 72: ...NC NC V I O GND NC 7 NC GND NC NC NC 6 NC NC EP3 3V PCI_PRES NC 5 NC GND CPCI_RST RSV NC 4 NC NC V I O HEALTHY NC 3 NC EP5V NC NC NC 2 NC NC NC 5V NC 1 5V 12V NC 12V 5V TABLE A 2 J1 Connector Description Signal Name Direction Basecard Signal Description Electrical Characteristics PCI_PRES Input Pull up on PWB tied low or left floating on backplane When low indicates that the backplane supports a C...

Page 73: ...ackplane i e E D C B A Figure A 2 shows the location of the contacts on the J2 connector FIGURE A 2 J2 Connector Table A 3 on page A 5 shows which signals are available from the J2 connector of the Compact CHAMP AV IV J1 J2 J3 J4 J5 J2 and J5 Connector Rear View A C D B F E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 S...

Page 74: ... NC NC NC 13 NC NC V I O GND NC 12 NC GND NC NC NC 11 NC NC V I O GND NC 10 NC GND NC NC NC 9 NC NC V I O GND NC 8 NC GND NC NC NC 7 NC NC V I O GND NC 6 NC GND NC NC NC 5 NC NC V I O GND NC 4 NC GND NC NC V I O 3 NC NC NC GND NC 2 NC NC NC NC NC 1 NC NC NC GND NC TABLE A 4 J2 Connector Description Signal Name Direction Description Electrical Characteristics GA 4 0 Input Signals are pulled to 3 3v...

Page 75: ...asecard Figure A 3 shows the location of contacts on the J3 connector FIGURE A 3 J3 Connector Note The pinout tables are presented in the order of the rows when looking from the backplane i e E D C B A J1 J2 J3 J4 J5 J3 Connector Rear View A C D B F E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 76: ..._TXN2 RC_TXP2 10 RC_RXN1 RC_RXP1 GND RC_TXN1 RC_TXP1 9 RC_RXN0 RC_RXP0 GND RC_TXN0 RC_TXP0 8 RB_RXN3 RB_RXP3 GND RB_TXN3 RB_TXP3 7 RB_RXN2 RB_RXP2 GND RB_TXN2 RB_TXP2 6 RB_RXN1 RB_RXP1 GND RB_TXN1 RB_TXP1 5 RB_RXN0 RB_RXP0 GND RB_TXN0 RB_TXP0 4 RA_RXN3 RA_RXP3 GND RA_TXN3 RA_TXP3 3 RA_RXN2 RA_RXP2 GND RA_TXN2 RA_TXP2 2 RA_RXN1 RA_RXP1 GND RA_TXN1 RA_TXP1 1 RA_RXN0 RA_RXP0 GND RA_TXN0 RA_TXP0 TABLE...

Page 77: ...plane i e E D C B A Figure A 4 shows the location of the contacts on the J4 connector FIGURE A 4 J4 Connector Tables A 7 and A 11 show which signals are available from the J4 connector of the Compact CHAMP AV IV J1 J2 J3 J4 J5 A C D B F E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 J1 and J4 Connector Rear View Artisan Technology Group Quality Instrumentation Guaranteed 888 8...

Page 78: ..._HRST 7 JTSEL GND GND 5V JP_CKSTPIN 6 NC GND GND JP_QREQ JP_TMS 5 JPROC2 3 3V GND NC JP_CKSTPO 4 JPROC0 3 3V GND 5V FL_WE 3 JPROC1 GND GND NC FL_RDYBSY 2 GND NC GND NC BCFG0 1 F_ALTPROM PBRST GND 3 3V BCFG1 TABLE A 8 J4 Connector Description Signal Name Direction Basecard Signal Description Electrical Characteristics CDxx DDxx Eexx Input Output Gigabit Ethernet signals comprised of Port C Port D a...

Page 79: ...Figure A 5 shows the location of contacts on the J5 connector FIGURE A 5 J5 Connector Note The pinout tables are presented in the order of the rows when looking from the backplane i e E D C B A J1 J2 J3 J4 J5 J2 and J5 Connector Rear View A C D B F E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 80: ...C_RXN1 LC_RXP1 GND LC_TXN1 LC_TXP1 13 LC_RXN0 LC_RXP0 GND LC_TXN0 LC_TXP0 12 LB_RXN3 LB_RXP3 GND LB_TXN3 LB_TXP3 11 LB_RXN2 LB_RXP2 GND LB_TXN2 LB_TXP2 10 LB_RXN1 LB_RXP1 GND LB_TXN1 LB_TXP1 9 LB_RXN0 LB_RXP0 GND LB_TXN0 LB_TXP0 8 LA_RXN3 LA_RXP3 GND LA_TXN3 LA_TXP3 7 LA_RXN2 LA_RXP2 GND LA_TXN2 LA_TXP2 6 LA_RXN1 LA_RXP1 GND LA_TXN1 LA_TXP1 5 LA_RXN0 LA_RXP0 GND LA_TXN0 LA_TXP0 4 RD_RXN3 RD_RXP3 G...

Page 81: ...CONNECTORS The Compact CHAMP AV IV PMC connectors are described in the following sections Note The direction of the signals in the tables describing the PMC Jn1 through Jn4 connectors is from the point of view of the baseboard Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 82: ...PCI PCI X 10 RESERVED N A RESERVED N A 11 GND N A GND GND 12 NC 3 3 V AUX N A No Connect 3 3 V Auxiliary Supply 3 3 V 13 PCICLK1 O PCI Clock Signal PCI PCI X 14 GND N A GND GND 15 GND N A GND GND 16 PMC1_GNT O Arbitration Grant Signal to PMC site 1 PCI PCI X 17 PMC1_REQ I Arbitration Request Signal from PMC site 1 PCI PCI X 18 5V N A Positive Supply 5V 19 VIO N A VIO Power see Note 1 5V or 3 3V 20...

Page 83: ...A GND GND 45 VIO N A VIO Power see Note 1 5V or 3 3V 46 AD 15 I O PCI Address Data Bus PCI PCI X 47 AD 12 I O PCI Address Data Bus PCI PCI X 48 AD 11 I O PCI Address Data Bus PCI PCI X 49 AD 09 I O PCI Address Data Bus PCI PCI X 50 5V N A Positive Supply 5V 51 GND N A GND GND 52 C BE 0 I O PCI Command Byte Enable Bus PCI PCI X 53 AD 06 I O PCI Address Data Bus PCI PCI X 54 AD 05 I O PCI Address Da...

Page 84: ... PPMC 12 3 3V N A Positive Supply 3 3V 13 RST O PCI Reset Signal PCI PCI X 14 BUSMODE3 O Basecard indicates PCI protocol used for PMC interface by driving this line low PMC PPMC 15 3 3V N A Positive Supply 3 3V 16 BUSMODE4 O Basecard indicates PCI protocol used for PMC interface by driving this line low PMC PPMC 17 RESERVED N A RESERVED N A 18 GND N A GND GND 19 AD 30 I O PCI Address Data Bus PCI ...

Page 85: ... X 48 AD 10 I O PCI Address Data Bus PCI PCI X 49 AD 08 I O PCI Address Data Bus PCI PCI X 50 3 3V N A Positive Supply 3 3V 51 AD 07 I O PCI Address Data Bus PCI PCI X 52 REQB I arbitration request signal for second PCI agent PCI PCI X 53 3 3V N A Positive Supply 3 3V 54 GNTB O arbitration grant signal for second PCI agent PCI PCI X 55 RESERVED N A RESERVED N A 56 GND N A GND GND 57 RESERVED N A R...

Page 86: ... PCI Parity Signal PCI PCI X 11 AD 63 I O PCI Address Data Bus PCI PCI X 12 AD 62 I O PCI Address Data Bus PCI PCI X 13 AD 61 I O PCI Address Data Bus PCI PCI X 14 GND N A GND GND 15 GND N A GND GND 16 AD 60 I O PCI Address Data Bus PCI PCI X 17 AD 59 I O PCI Address Data Bus PCI PCI X 18 AD 58 I O PCI Address Data Bus PCI PCI X 19 AD 57 I O PCI Address Data Bus PCI PCI X 20 GND N A GND GND 21 VIO...

Page 87: ... O PCI Address Data Bus PCI PCI X 44 GND N A GND GND 45 GND N A GND GND 46 AD 40 I O PCI Address Data Bus PCI PCI X 47 AD 39 I O PCI Address Data Bus PCI PCI X 48 AD 38 I O PCI Address Data Bus PCI PCI X 49 AD 37 I O PCI Address Data Bus PCI PCI X 50 GND N A GND GND 51 GND N A GND GND 52 AD 36 I O PCI Address Data Bus PCI PCI X 53 AD 35 I O PCI Address Data Bus PCI PCI X 54 AD 34 I O PCI Address D...

Page 88: ...dule 13 I O PMC 1 connection to cPCI J5 connector Depends on module 14 I O PMC 1 connection to cPCI J5 connector Depends on module 15 I O PMC 1 connection to cPCI J5 connector Depends on module 16 I O PMC 1 connection to cPCI J5 connector Depends on module 17 I O PMC 1 connection to cPCI J5 connector Depends on module 18 I O PMC 1 connection to cPCI J5 connector Depends on module 19 I O PMC 1 conn...

Page 89: ...cPCI J5 connector Depends on module 49 I O PMC 1 connection to cPCI J5 connector Depends on module 50 I O PMC 1 connection to cPCI J5 connector Depends on module 51 I O PMC 1 connection to cPCI J5 connector Depends on module 52 I O PMC 1 connection to cPCI J5 connector Depends on module 53 I O PMC 1 connection to cPCI J5 connector Depends on module 54 I O PMC 1 connection to cPCI J5 connector Depe...

Page 90: ...e PCI PCI X 10 RESERVED N A RESERVED N A 11 GND N A GND GND 12 NC 3 3 V AUX N A No Connect 3 3V Auxiliary Supply 3 3 V 13 PCICLK2 O PCI Clock Signal PCI PCI X 14 GND N A GND GND 15 GND N A GND GND 16 PMC2_GNT O Arbitration Grant Signal to PMC site 2 PCI PCI X 17 PMC2_REQ I Arbitration Request Signal from PMC site 2 PCI PCI X 18 5V N A Positive Supply 5 V 19 VIO N A VIO Power see Note 1 5 V or 3 3V...

Page 91: ... 45 VIO N A VIO Power see Note 1 5 V or 3 3V 46 AD 15 I O PCI Address Data Bus PCI PCI X 47 AD 12 I O PCI Address Data Bus PCI PCI X 48 AD 11 I O PCI Address Data Bus PCI PCI X 49 AD 09 I O PCI Address Data Bus PCI PCI X 50 5V N A Positive Supply 5V 51 GND N A GND GND 52 C BE 0 I O PCI Command Byte Enable Bus PCI PCI X 53 AD 06 I O PCI Address Data Bus PCI PCI X 54 AD 05 I O PCI Address Data Bus P...

Page 92: ...PMC PPMC 12 3 3V N A Positive Supply 3 3V 13 RST O PCI Reset Signal PCI PCI X 14 BUSMODE3 O Basecard indicates PCI protocol used for PMC interface by driving this line low PMC PPMC 15 3 3V N A Positive Supply 3 3V 16 BUSMODE4 O Basecard indicates PCI protocol used for PMC interface by driving this line low PMC PPMC 17 RESERVED N A RESERVED N A 18 GND N A GND GND 19 AD 30 I O PCI Address Data Bus P...

Page 93: ...48 AD 10 I O PCI Address Data Bus PCI PCI X 49 AD 08 I O PCI Address Data Bus PCI PCI X 50 3 3V N A Positive Supply 3 3V 51 AD 07 I O PCI Address Data Bus PCI PCI X 52 REQB I arbitration request signal for second PCI agent PCI PCI X 53 3 3V N A Positive Supply 3 3V 54 GNTB O arbitration grant signal for second PCI agent PCI PCI X 55 RESERVED N A RESERVED N A 56 GND N A GND GND 57 RESERVED N A RESE...

Page 94: ...PAR64 I O PCI Parity Signal PCI PCI X 11 AD 63 I O PCI Address Data Bus PCI PCI X 12 AD 62 I O PCI Address Data Bus PCI PCI X 13 AD 61 I O PCI Address Data Bus PCI PCI X 14 GND N A GND GND 15 GND N A GND GND 16 AD 60 I O PCI Address Data Bus PCI PCI X 17 AD 59 I O PCI Address Data Bus PCI PCI X 18 AD 58 I O PCI Address Data Bus PCI PCI X 19 AD 57 I O PCI Address Data Bus PCI PCI X 20 GND N A GND G...

Page 95: ...43 AD 41 I O PCI Address Data Bus PCI PCI X 44 GND N A GND GND 45 GND N A GND GND 46 AD 40 I O PCI Address Data Bus PCI PCI X 47 AD 39 I O PCI Address Data Bus PCI PCI X 48 AD 38 I O PCI Address Data Bus PCI PCI X 49 AD 37 I O PCI Address Data Bus PCI PCI X 50 GND N A GND GND 51 GND N A GND GND 52 AD 36 I O PCI Address Data Bus PCI PCI X 53 AD 35 I O PCI Address Data Bus PCI PCI X 54 AD 34 I O PCI...

Page 96: ...o cPCI J5 connector Depends on module 14 I O PMC 2 connection to cPCI J5 connector Depends on module 15 I O PMC 2 connection to cPCI J5 connector Depends on module 16 I O PMC 2 connection to cPCI J5 connector Depends on module 17 I O PMC 2 connection to cPCI J3 connector Depends on module 18 I O PMC 2 connection to cPCI J3 connector Depends on module 19 I O PMC 2 connection to cPCI J3 connector De...

Page 97: ...le 49 I O PMC 2 connection to cPCI J3 connector Depends on module 50 I O PMC 2 connection to cPCI J3 connector Depends on module 51 I O PMC 2 connection to cPCI J3 connector Depends on module 52 I O PMC 2 connection to cPCI J3 connector Depends on module 53 I O PMC 2 connection to cPCI J3 connector Depends on module 54 I O PMC 2 connection to cPCI J3 connector Depends on module 55 I O PMC 2 connec...

Page 98: ... 20 A16 B16 42 18 20 A12 B12 11 21 23 D15 E15 43 21 23 D11 E11 12 22 24 A15 B15 44 22 24 A11 B11 13 25 27 D14 E14 45 25 27 D10 E10 14 26 28 A14 B14 46 26 28 A10 B10 15 29 31 D13 E13 47 29 31 D9 E9 16 30 32 A13 B13 48 30 32 A9 B9 17 33 35 D12 E12 49 33 35 D8 E8 18 34 36 A12 B12 50 34 36 A8 B8 19 37 39 D11 E11 51 37 39 D7 E7 20 38 40 A11 B11 52 38 40 A7 B7 21 41 43 D10 E10 53 41 43 D6 E6 22 42 44 A1...

Page 99: ...20 E 35 E12 E8 4 B20 B 36 B12 B8 5 D19 D 37 D11 D7 6 A19 A 38 A11 A7 7 E19 E 39 E11 E7 8 B19 B 40 B11 B7 9 D18 D 41 D10 D6 10 A18 A 42 A10 A6 11 E18 E 43 E10 E6 12 B18 B 44 B10 B6 13 D17 D 45 D9 D5 14 A17 A 46 A9 A5 15 E17 E 47 E9 E5 16 B17 B 48 B9 B5 17 D16 D cPCI Connector J3 PMC 2 only 49 D8 D4 18 A16 A 50 A8 A4 19 E16 E 51 E8 E4 20 B16 B 52 B8 B4 21 D15 D 53 D7 D3 22 A15 A 54 A7 A3 23 E15 E 55...

Page 100: ... 1 18 F feature summary 1 4 Flash memory 1 7 G general description 1 1 General Purpose I O and interrupt inputs 1 16 H hardware requirements 2 2 high speed SRAM 1 7 I indicator LEDs 1 16 initial screen message 3 6 Initiate the Power Up Sequence 3 6 insert basecard in chassis 3 5 installation procedure summary 3 1 installing PMC modules 3 3 internal interrupt sources 1 11 interrupt routing 1 10 int...

Page 101: ...sor nodes 1 5 Q QuadFlow architecture 1 5 R reset 1 19 S serial communications connecting a terminal 3 5 serial port summary 1 17 serial ports 1 17 Sign on Message Garbled 3 10 slot location 3 3 software development tools 1 27 software overview 1 26 summary of Compact CHAMP AV IV connectors 1 24 SVME 424 Front Panel 1 23 T technical description 1 4 temperature voltage sensors 1 19 terminal setting...

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