CTI MPG401, User Manual

Page: 17 / 22

Mini PCIe ADC
Users Guide
www.connecttech.com
Document: CTIM-00149
Revision: 0.02 Page 17 of 22
Connect Tech Inc. 800-426-8979 | 519-836-1291
Date: 2018-10-25
Common Features
The following section describes several of the board level common features, including the interrupt controller
and ID register.
Memory Map
Block Offset
(Hex)
0x03 0x02 0x01 0x00
COMMON_BASE 0xC IRQ_STATUS
COMMON_BASE 0x18 SCRATCHPAD_REG_1
COMMON_BASE 0x1C SCRATCHPAD_REG_2
ID_BASE 0x0 RELEASE
ID_BASE 0x4 TIMESTAMP
IRQ_BASE 0x40 IRQ_MSTR_STATUS
IRQ_BASE 0x50 IRQ_MSTR_ENABLE
Register Details
IRQ_ STATUS (
COMMON_BASE
+0x0C – Read/Write)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Not used
A
D
C
1
A
D
C
0
ADC0 ADC controller block 0 has a FIFO over the trigger level
ADC1 ADC controller block 1 has a FIFO over the trigger level
The register must be written to in order to clear the flag. Currently there is only one interrupt source per ADC
block, which makes IRQ_MSTR_STATUS seem redundant.
SCRATCHPAD_REG_1 (COMMO0x18 – Read/Write)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Test value
A scratch pad register for software testing.
SCRATCHPAD_REG_2 (COMMO0x1C – Read/Write)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Test value
A scratch pad register for software testing.