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Mini PCIe ADC

Users Guide

www.connecttech.com

Document: CTIM-00149
Revision: 0.02

Page 16 of 22

Connect Tech Inc. 800-426-8979 | 519-836-1291

Date: 2018-10-25

Flash Controller

Overview

The Mini PCIe ADC has a built-in flash controller to facilitate remote updates over the Mini PCIe bus.   There
are two usage modes – update flash and cold boot reconfig or update flash and live reconfiguration.

Update flash and cold boot – the flash is erased and a new configuration image is written then verified.  The
FPGA is not update until the next power cycle.

Update flash and liver reconfiguration – the flash is erased and new configuration image is written then
verified.  The PCIe configuration registers are then save, the a configuration cycle is initiated, and the PCIe
configuration registers are restored.

Operation

For futher details on the flash controller operation, contact [email protected] to obtain the necessary
software package.

Memory Map

Offset

(Hex)

0x03

0x02

0x01

0x00

0x0000 SPI_CMD

0x0004 SPI_PARAM

0x0008 SPI_STATUS

0x000C SPI_RESULT

0x00100 SPI_PAGE_MEM

Register Details

For futher details on the flash controller operation, contact [email protected] to obtain the necessary
software package.

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Summary of Contents for MPG401

Page 1: ...Tech Inc Tel 519 836 1291 42 Arrow Road Toll 800 426 8979 North America only Guelph Ontario Fax 519 836 4878 N1K 1S6 Email sales connecttech com www connecttech com support connecttech com CTIM 00149 Revision 0 02 2018 10 25 ...

Page 2: ...eneral Board Operation 9 Interfacing Convention 9 Memory Map 9 Analog Inputs ADCs 10 Overview 10 Connectors Jumpers 10 Operation 10 Continuous Sampling Mode 11 Waveform Capture Mode FIFO Mode 11 Variable Sampling Rate 11 Memory Map 12 Register Details 12 CONTROL_CONFIG ADC Offset 0x0000 Read Write 12 INPUT_RANGE_SELECT ADC Offset 0x0010 Read Write 12 CHx_LAST_SAMPLE Offset 0x0014 Read Only 13 MEM_...

Page 3: ... COMMON_BASE 0x1C Read Write 17 IRQ_MSTR_STATUS IRQ_BASE 0x40 Read Only 18 IRQ_MSTR_ENABLE IRQ_BASE 0x50 Read Write Only 18 RELEASE ID_BASE 0x0 Read Only 18 TIMESTAMP ID_BASE 0x4 Read Only 18 Application Examples 19 Example A writing reading from scratch pad 19 Example B reading ID registers 19 Software Installation 20 Typical Installation 20 Appendix A Header File 21 ...

Page 4: ...upport section is available 24 hours a day 7 days a week on our website at www connecttech com sub support support asp See the contact information section below for more information on how to contact us directly Our technical support is always free Contact Information Mail Courier Connect Tech Inc Technical Support 42 Arrow Road Guelph Ontario Canada N1K 1S6 Email Internet sales connecttech com su...

Page 5: ... the product prove to be irreparable Connect Tech Inc reserves the right to substitute an equivalent product if available or to retract the Warranty if no replacement is available The above warranty is the only warranty authorized by Connect Tech Inc Under no circumstances will Connect Tech Inc be liable in any way for any damages including any lost profits lost savings or other incidental or cons...

Page 6: ...ds in their antistatic packaging until they are ready to be installed Using a grounded wrist strap when handling circuit boards at a minimum you should touch a grounded metal object to dissipate any static charge that may be present on you Only handling circuit boards in ESD safe areas which may include ESD floor and table mats wrist strap stations and ESD safe lab coats Avoiding handling circuit ...

Page 7: ...ll sized Host Interface Bus PCI Express Gen 1 0 Analog Inputs Channels 16 Single Ended Resolution 16 bit Sampling Rate 500ksps Protection 20V Input Ranges Bipolar 10 24V 5 12V and 2 56V Unipolar 0 10 24V and 0 5 12V Accuracy 2 5 LSB INL 1 5 LSB DNL Signal to Noise Ratio 91 dB 10 24V Operating Temperature 40 to 85 Degrees Celsius Dimensions 50 95mm x 30mm Mini PCIe Full Power Consumption 3 3VDC 0 3...

Page 8: ...interfaces Each SPI bus is independent and managed by separate control block Connection to analog signals is provided by single high density latching connector Block Diagram Connector Summary Locations Designator Description P1 Analog Inputs P5 JTAG programming Jumper Summary Locations This board is completely jumper less all options are configured through software Altera Cyclone IV GX FPGA TI 16 ...

Page 9: ...d from a separate base address location however the registers within those blocks have identical functionality There are separate memory blocks for the interrupt controller on board flash programming controller and board identification Memory Map The following table shows the overall memory map Offset Identifier Description 0x0000 COMMON_BASE General Board control 0x1000 ADC0 Analog to Digital Con...

Page 10: ... 7 ADC0_CH4 8 ADC0_CH5 9 ADC0_CH6 10 ADC0_CH7 11 ADC1_CH0 12 ADC1_CH1 13 ADC1_CH2 14 ADC1_CH3 15 ADC1_CH4 16 ADC1_CH5 17 GND 18 GND 19 ADC1_CH6 20 ADC1_CH7 Operation The ADCs are controlled and have their data stored in two controller blocks The mode of capture can be set to either Continuous Sampling Mode or Waveform Capture Mode The input range for each of the 4 ADCs can be changed via the INPUT...

Page 11: ...and the sample number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 bit Timestamp Sample Num R Channel ID 16 bit CODE from ADC For example to set up an ADC block to capture data in its sample FIFO and provide a notification once it has stored 1023 of these values one would write 0x3FF to the first ten bits of its MEM_WRITE_CONTROL register and then set th...

Page 12: ...8 CHANNEL_ID TIMESTAMP_2 MEM_SAMPLE_2 0x2FFC CHANNEL_ID TIMESTAMP_4k MEM_SAMPLE_2k Register Details CONTROL_CONFIG ADC Offset 0x0000 Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Future Use S T O P R S T D I V S T O R S C H 0 S C H 1 S C H 2 S C H 3 S C H 4 S C H 5 S C H 6 S C H 7 This register contains several control bits flags STOP 0 n...

Page 13: ...s register contains the last sampled 16 bit code for the specific channel Bit 15 is the MSB of the CODE and Bit 0 is the LSB for the CODE All samples are in a binary format for both bipolar and unipolar input ranges The full scale range FSR for each input signal is equal to the difference between the positive full scale PFS input voltage and the negative full scale NFS input voltage The LSB size i...

Page 14: ...range In this example we will set the 2 ADC IC s to enable sampling and set the input range for each of the ADCs to be 10 24V Then we will read back all the channels printf ADC0 1 enabling chan0 7 and setting input range n control_config 0xFF CTIFPGAWrWord pbrd BarIndex ADC0 CONTROL_CONFIG control_config CTIFPGAWrWord pbrd BarIndex ADC1 CONTROL_CONFIG control_config input_range 0x0 CTIFPGAWrDword ...

Page 15: ...fig CTIFPGAWrWord pbrd BarIndex ADC1 CONTROL_CONFIG control_config input_range 0x0 CTIFPGAWrDword pbrd BarIndex ADC0 INPUT_RANGE_SELECT input_range input_range 0x0 for ch 0 ch 8 ch input_range 0x5 3 ch CTIFPGAWrDword pbrd BarIndex ADC1 INPUT_RANGE_SELECT input_range printf nReading ADC Voltages n i 0 CTIFPGARdWord pbrd BarIndex ADC0 CH0_LAST_SAMPLE i 2 testreg ADC0votlage testreg 20 48 0x10000 0x8...

Page 16: ...s not update until the next power cycle Update flash and liver reconfiguration the flash is erased and new configuration image is written then verified The PCIe configuration registers are then save the a configuration cycle is initiated and the PCIe configuration registers are restored Operation For futher details on the flash controller operation contact support connecttech com to obtain the nec...

Page 17: ...0x0C Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not used A D C 1 A D C 0 ADC0 ADC controller block 0 has a FIFO over the trigger level ADC1 ADC controller block 1 has a FIFO over the trigger level The register must be written to in order to clear the flag Currently there is only one interrupt source per ADC block which makes IRQ_MSTR_STATUS see...

Page 18: ...RQ_MSTR_ENABLE IRQ_BASE 0x50 Read Write Only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not used F L A S H A D C 1 A D C 0 ADC0 ADC controller block 0 interrupt is enabled ADC1 ADC controller block 1 interrupt is enabled FLASH SPI Flash controller block interrupt is enabled This is the overall interrupt enable for each functional block To mask an interrup...

Page 19: ...OMMON_BASE SCRATCHPAD_REG_1 rdreg if ret CTI_STATUS_OK printf Error read from FPGA mem result FALSE else printf rd reg 0x 08x n rdreg if wrreg rdreg printf Expected x read x n wrreg rdreg Example B reading ID registers printf reading ID registers n time_t rawtime struct tm timeinfo ret CTIFPGARdDword pbrd BAR_MAIN ID_BASE 0x0 idreg if ret CTI_STATUS_OK printf Error read from FPGA mem result FALSE ...

Page 20: ...wnloadZone_results asp Product 37 The UFD is available for multiple operating systems refer to the website for availability and check back for the latest releases Typical Installation 1 Ensure the target system is powered off 2 Insert the Mini PCIe ADC into standard Mini PCIe full sized slot clip or screw into place depending on the available mounting hardware 3 Attached the application cabling to...

Page 21: ...fine ADC1 0x4000 define CONTROL_CONFIG 0x0 define STATUS 0x4 define CLK_DIV 0x8 define CLK_DIV_CNTR 0xC define INPUT_RANGE_SELECT 0x10 define CH0_LAST_SAMPLE 0x14 define CH1_LAST_SAMPLE 0x14 2 define CH2_LAST_SAMPLE 0x18 define CH3_LAST_SAMPLE 0x18 2 define CH4_LAST_SAMPLE 0x1C define CH5_LAST_SAMPLE 0x1C 2 define CH6_LAST_SAMPLE 0x20 define CH7_LAST_SAMPLE 0x20 2 define MEM_WR_CONTROL 0x24 define...

Page 22: ... Users Guide www connecttech com Document CTIM 00149 Revision 0 02 Page 22 of 22 Connect Tech Inc 800 426 8979 519 836 1291 Date 2018 10 25 define IRQ_MSTR_ENABLE 0x50 define IRQBIT_ADC0 0x00 define IRQBIT_ADC1 0x01 ...

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