Corvalent Gator Mini-ITX, Installation Manual

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Gator Mini-ITX – Installation Guide
D8 The Runtime module is uncompressed into memory. CPUID information is stored in
memory.
D9 Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory.
Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but
closing SMRAM.
DA Restore CPUID value back into register. Give control to BIOS POST
(ExecutePOSTKernel). See POST Code Checkpoints section of document for more
information.
E1-E8 EC-EE OEM memory detection/configuration error. This range is reserved for chipset vendors &
system manufacturers.
Table B-2 Bootblock Recovery Code Checkpoints
The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because
the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of
checkpoints that may occur during the Bootblock recovery portion of the BIOS:
Checkpoint Code Description
E0 Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA
controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.
E9 Set up floppy controller and data. Attempt to read from floppy.
EA Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
EB Disable ATAPI hardware. Jump back to checkpoint E9.
EF Read error occurred on media. Jump back to checkpoint EB.
F0 Search for pre-defined recovery file name in root directory.
F1 Recovery file not found.
F2 Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.
E0 Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA
controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.
E9 Set up floppy controller and data. Attempt to read from floppy.
EA Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
EB Disable ATAPI hardware. Jump back to checkpoint E9.
EF Read error occurred on media. Jump back to checkpoint EB.
F0 Search for pre-defined recovery file name in root directory.
F1 Recovery file not found.
F2 Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.
Table B-3 POST Code Checkpoints
The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. The following
table describes the type of checkpoints that may occur during the POST portion of the BIOS:
Checkpoint Code Description
03 Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST,
Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized
CMOS as mentioned in the Kernel Variable "wCMOSFlags."
04 Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is
OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is
bad, update CMOS with power-on default values and clear passwords. Initialize status
register A.
Initializes data variables that are based on CMOS setup questions. Initializes both the 8259
compatible PICs in the system
05 Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06 Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch
handler. Enable IRQ-0 in PIC for system timer interrupt.
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