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Appendix A: Technical Specifications

Table A-20 J4 LVDS Connector

Pin#

LVDS – J4

1 GND
2

LVDS VDD 3.3V

3

LVDS VDD 3.3V

4

LVDS DDC VCC 3.3V

5 NC
6 DDC

CLK

7 DDC

DATA

8 LVDS

YAM0

9 LVDS

YAP0

10 GND
11 LVDS

YAM1

12 LVDS

YAP1

13 GND
14 LVDS

YAM2

15 LVDS

YAP2

16 GND
17

LVDS CLK AM

18

LVDS CLK AP

19 GND
20 LVDS

YBM0

21 LVDS

YBP0

22 GND
23 LVDS

YBM1

24 LVDS

YBP1

25 GND
26 LVDS

YBM2

27 LVDS

YBP2

28 GND
29

LVDS CLK BM

30

LVDS CLK BP

43

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Summary of Contents for Gator Mini-ITX

Page 1: ... Gator Mini ITX Motherboard Installation Guide ...

Page 2: ......

Page 3: ...ator Mini ITX Memory Configuration 5 CPU Installation 5 Installing Cables 6 Power and Control Panel Cables 6 Installing Peripheral Cables 7 Index of Connectors 9 Chapter 2 AMIBIOS8 Setup 11 Main Setup 14 Advanced BIOS Setup 14 PCI PnP Setup 22 Boot Setup 24 Security Setup 26 Chipset Setup 27 Power Management Setup 29 Exit Menu 30 Chapter 3 Upgrading 31 Upgrading the Microprocessor 31 Upgrading the...

Page 4: ...rrupt Routing Map 37 Connectors Pin out 38 Appendix B Flash BIOS programming and codes 45 Troubleshooting POST 45 Critical Error BEEP Codes 49 Appendix C On Board Industrial Devices 51 DC power brick connector 51 On board Ethernet 51 Serial Ports 51 Watchdog Timer 56 Appendix On Board Video Controller 57 II ...

Page 5: ...blication and any accompanying software may not in whole or in part be copied photocopied translated or reduced to any machine readable form without prior consent from the vendor manufacturer or creators of this publication except for copies kept by the user for backup purposes Brand and product names mentioned in this publication may or may not be copyrights and or registered trademarks of their ...

Page 6: ...ion This chapter provides all the necessary information for installing the Gator Mini ITX Topics discussed include installing the CPU if necessary DRAM installation and jumper settings Connecting all the cables from the system board to the chassis and peripherals is also explained Chapter 2 BIOS Configuration This chapter shows the final step in getting your system firmware setup Chapter 3 Upgradi...

Page 7: ...her than the manufacturer or if failure is caused by accident acts of God or other causes beyond the manufacturer s control Gator Mini ITX An Overview The Gator Mini ITX represents the ultimate in industrial embedded motherboard technology No other system board available today provides such impressive list of features CPU Support Supports low power low profile series of Intel Pentium M and Celeron...

Page 8: ...B AC97 compliant Microphone In Stereo Line In and Out Stereo Headphone Out and CD In On board watchdog timer ROM BIOS American Megatrends AMIBIOS8 with FLASH ROM On Board CRT LVDS video controller Standard CRT video controller Intel 855GME chipset Optional dedicated Local Flat Panel LFP LVDS interface Conventions Used in this Manual Notes Such as a brief discussion of memory types Important Inform...

Page 9: ...ent leads rendering the board unusable Always handle the Gator Mini ITX with care Special Warranty Note Products returned for warranty repair will be inspected for damage caused by improper installation and misuse as described in the previous section and the static warning below Should the board show signs of abuse the warranty will become void and the customer will be billed for all repairs and s...

Page 10: ... two different categories of jumpers on the Gator Mini ITX A Two pin jumpers are used for binary selections such as enable disable Instructions for this type of jumper are open for no shunt over the pins or closed when the shunt covers the pins B Three or four pin jumpers are used for multiple selections Instructions for these jumpers will indicate which two pins to cover For example for JPx 2 3 t...

Page 11: ...Chapter 1 Pre Configuration Jumper Locations Use the diagram below and the tables on the following pages to locate and set the on board configuration jumpers Figure 1 1 Jumper Locations 3 ...

Page 12: ...ion Resistors optional The Jumper JP6 allows the insertion removal of the termination resistors 120Ω in the Receiver and Transmitter lines of the COM1 when operating in RS 422 485 mode Table 1 3 COM1 RS 422 485 Tx Rx Termination Resistor Selection Termination resistor selection Transmitter Receiver JP6 1 3 2 4 Manufacturer s Setting is off Audio Jack Output Selection The audio output on the jack c...

Page 13: ...fers 2 DIMM memory sockets Locations J1 and J2 Figure 1 3 They can be configured with 2 5V unbuffered SDRAM DDR modules It is very important that the quality of the DIMMs is good Unreliable operation of the system may result if poor quality DIMMs are used Always purchase your memory from a reliable source Please refer to chapter 3 for memory details CPU Installation The Gator Mini ITX currently su...

Page 14: ...y care must be taken to avoid improper thermal management All Intel thermal solution specifications design guidelines and suggestions to the CPU being used must be followed The Gator Mini ITX warranty is void if the thermal management does not comply with Intel requirements Designing for thermal performance In designing for thermal performance the goal is to keep the processor within the operation...

Page 15: ...long leg of the cable must be connected to the board otherwise it won t work as an 80 conductor cable If connecting another peripheral that is not UDMA 5 capable most optical devices are not the whole IDE channel will be downgraded to UDMA 2 In that case it is recommended to use a different IDE channel for the non UDMA 5 capable peripherals Connect the floppy cable not included to the system board...

Page 16: ...Gator Mini ITX Installation Guide Figure 1 3 Location of Components and Connectors 8 ...

Page 17: ...dex of Connectors Please refer to Appendix A for pin out descriptions Table 1 7 Connectors description Connector Description J1 DDR DIMM Socket 0 J2 DDR DIMM Socket 1 J3A VGA DB15 J3B Audio Line Out Headphone Out J3C Audio Line In 9 ...

Page 18: ...2 J20A COM3 Optional J20B COM4 Optional J20C COM5 Optional J20D COM6 Optional J24 Floppy Disk Drive Connector J25 Keyboard Mouse PS 2 J26 CPU Fan J27 Rear Chassis Fan J28 Front Panel Header J29 Optional 12VDC Power Brick Connector J30 ATX Power Connector J31 Floppy Power Connector J32 Front Panel Header IR JP7 External RTC CMOS Battery S1 PCI Connector S2 PCI Riser Connector U2 CPU Socket U13A Eth...

Page 19: ...OS Starting BIOS Setup AMIBIOS has been integrated into many motherboards for over a decade In the past people often referred to the AMIBIOS setup menu as BIOS BIOS setup or CMOS setup American Megatrends refers to this setup as ezPORT Specifically it is the name of theAMIBIOS8 BIOS setup utility This chapter describes the basic navigation of the ezPORT setup screens To enter the ezPORT setup scre...

Page 20: ...zPORT key legend by default To set the Fail Safe settings of the BIOS press the F8 key on your keyboard It is located on the upper row of a standard 101 keyboard The Fail Safe settings allow the motherboard to boot up with the least amount of options set This can lessen the probability of conflicting settings 12 ...

Page 21: ...Chapter 2 BIOS Configuration 13 ...

Page 22: ...screen to select options for the IDE Configuration Settings Use the up and down Arrow keys to select an item Use the Plus and Minus keys to change the value of the selected option A description of the selected item appears on the right side of the screen Onboard PCI IDE Controller This item specifies the IDE channels used by the onboard PCI IDE controller The settings are Disabled Primary Secondar...

Page 23: ...ing when all IDE connectors are set to AUTO in the AMIBIOS setting Note Different IDE disk drives take longer for the BIOS to locate than others do ATA PI 80 pin Cable Detection Set this option to select the method used to detect the ATA PI 80 pin cable The Optimal and Fail Safe setting is Host Device Host Device Set this value to use both the motherboard onboard IDE controller and IDE disk drive ...

Page 24: ...ve capacities over 137 GB Disabled Set this value to prevent the BIOS from using Large Block Addressing mode control on the specified channel Auto Set this value to allow the BIOS to auto detect the Large Block Addressing mode control on the specified channel This is the default setting Block Multi Sector Transfer This option sets the block mode multi sector transfers option The Optimal and Fail S...

Page 25: ...his is the default setting Disabled Set this value to prevent the BIOS from using the SMART feature Enabled Set this value to allow the BIOS to use the SMART feature on support hard disk drives 32Bit Data Transfer This option sets the 32 bit data transfer option The Optimal and Fail Safe default setting is Enabled Disabled Set this value to prevent the BIOS from using 32 bit data transfers Enabled...

Page 26: ...o use 2F8 as its I O port address If the system will not use a serial device it is best to set this port to Disabled 3E8 Set this value to allow the serial port to use 3E8 as its I O port address If the system will not use a serial device it is best to set this port to Disabled 2E8 Set this value to allow the serial port to use 2E8 as its I O port address If the system will not use a serial device...

Page 27: ...l port5 is disabled 3 4 5 6 7 10 11 Serial Port6 Address This option specifies the base I O port address of serial port 6 The default setting is Disabled Disabled 3E8 2E8 338 238 228 220 Serial Port6 IRQ This option specifies the IRQ of serial port 6 This option is not available if serial port6 is disabled 3 4 5 6 7 10 11 Parallel Port Address This option specifies the I O address used by the para...

Page 28: ... item Use the Plus and Minus keys to change the value of the selected option Advanced ACPI Configuration You can use this screen to select options for the ACPI Advanced Configuration Settings Use the up and down Arrow keys to select an item Use the Plus and Minus keys to change the value of the selected option A description of the selected item appears on the right side of the screen ACPI Version ...

Page 29: ... value of the selected option PCI Error Logging Enables or disables PCI Error logging The Optimal and Fail Safe default setting is Disabled Enabled Disabled USB CONFIGURATION SCREEN USB Configuration Screen You can use this screen to select options for the USB Configuration Use the up and down Arrow keys to select an item Use the Plus and Minus keys to change the value of the selected option USB F...

Page 30: ... setting is Yes No The No setting is for operating systems that do not meet the Plug and Play specifications It allows the BIOS to configure all the devices in the system Yes The Yes setting allows the operating system to change the interrupt I O and DMA settings Set this option if the system is running Plug and Play aware operating systems PCI Latency Timer Set this value to allow the PCI Latency...

Page 31: ... as the location of the OffBoard PCI IDE adapter card Use this setting only if there is an IDE adapter card installed in PCI Slot 2 IRQ Set this value to allow the IRQ settings to be modified The Optimal and Fail Safe default setting is Available IRQ3 IRQ4 IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 Available This setting allows the specified IRQ to be used by a PCI PnP device This is the default setti...

Page 32: ...d party BIOS to display during system boot This is the default setting Keep Current Set this value to allow the computer system to display the ezPORT information during system boot Boot up Num Lock Set this value to allow the Number Lock setting to be modified during boot up The Optimal and Fail Safe default setting is Off Off This option does not enable the keyboard Number Lock automatically To u...

Page 33: ...ORITY Boot Device Priority Use this screen to specify the order in which the system checks for the device to boot from To access this screen select Boot Device Priority on the Boot Setup screen and press Enter 1st Boot Device 2nd Boot Device 3rd Boot Device Set the boot device options to determine the sequence in which the computer checks which device to boot from The settings are Removable Dev Ha...

Page 34: ... described in this section To access the sub menu for the following items select the item and press Enter Change Supervisor Password Change User Password Clear User Password Supervisor Password Indicates whether a supervisor password has been set If the password has been installed Installed displays If not Not Installed displays User Password Indicates whether a user password has been set If the p...

Page 35: ...s not display the characters entered Retype the password as prompted and press Enter If the password confirmation is incorrect an error message appears The password is stored in NVRAM after ezPORT completes Deleting a Password If you forget the passwords you set up through ezPORT Setup the only way you can reset the password is to erase the system configuration information where the passwords are ...

Page 36: ...ble the internal graphics engine and allocate 8MB of system memory for it This is the default setting Enabled 16MB This setting will enable the internal graphics engine and allocate 16MB of system memory for it Enabled 32MB This setting will enable the internal graphics engine and allocate 32MB of system memory for it IGD Device 2 Function 1 Enable or Disable the internal graphics device by settin...

Page 37: ...OFF This setting will keep the CPU board OFF when A C power is reestablished To turn the board ON the power button must be used Last State This setting will put the CPU board back to its state before the accidental power failure It requires ACPI enabled and an ACPI capable OS The board must be normally turned OFF through a controlled S5 soft OFF Power button transition if it is not an accidental p...

Page 38: ...Ok to discard changes and exit Load Optimal Defaults ezPORT automatically sets all ezPORT Setup options to a complete set of default settings when you Select this option The Optimal settings are designed for maximum system performance but may not work best for all computer applications In particular do not use the Optimal ezPORT Setup options if your computer is experiencing system configuration p...

Page 39: ...esult if poor quality DIMMs are used Always purchase your memory from a reliable source System Memory Features 2 5 V only 184 pin DDR SDRAM DIMMs with gold plated contacts Unbuffered unregistered single sided or double sided DIMMs Maximum total system memory 2 GB minimum total system memory 32 MB DDR333 MHz PC2700 and DDR266 MHz PC2100 DDR SDRAM DIMMs only Serial Presence Detect SPD You can use EC...

Page 40: ...he ICH4 Parallel ATA IDE controller has two independent bus mastering Parallel ATA IDE interfaces that can be independently enabled The Parallel ATA IDE interfaces support the following modes Programmed I O PIO processor controls data transfer 8237 style DMA DMA offloads the processor supporting transfer rates of up to 16 MB sec Ultra DMA DMA protocol on IDE bus supporting host and target throttli...

Page 41: ... One device can be installed on each port for a maximum of two Serial ATA devices A point to point interface is used for host to device connections unlike Parallel IDE which supports a master slave configuration and two devices per channel For compatibility the underlying Serial ATA functionality is transparent to the operating system NOTE Many Serial ATA drives use new low voltage power connector...

Page 42: ... battery Connector for external connection Control Panel Connections Reset Soft Power LEDs for power and IDE CPU Socket Standard ZIF Zero Insertion Force µFC PGA 478 Form Factor Mini ITX form factor 6 7 x 6 7 PCB Construction Twelve Layers dry film mask Manufacturing Process Automated surface mount Table A 1 Environmental Environmental Operating Non operating Temperature 0 to 55 C 40 to 65 C Humid...

Page 43: ...urce 0 8 or 16 bits 1 8 or 16 bits Parallel port for ECP if selected 2 8 or 16 bits Floppy Drive 3 8 or 16 bits Parallel port for ECP if selected 4 Reserved cascade channel 5 16 bits Open 6 16 bits Open 7 16 bits Open I O Map Address hex Description 0000 000F DMA 1 0020 0021 Interrupt Controller 1 0040 Timer Counter 0 0041 Timer Counter 1 0042 Timer Counter 2 0043 Timer Control Word 0060 Keyboard ...

Page 44: ... Channel 1 03F6 Primary IDE channel command port 03F7 Floppy Channel 1 command 03F7 bit 7 Floppy disk change channel 1 03F7 bits 6 0 Primary IDE channel status report 03F8 03FF COM1 default 0CF8 0CFB 4 bytes PCI configuration address register 0CF9 Reset control register 0CFC 0CFF 4 bytes PCI configuration data register PCI Configuration Space Map Bus Device Function Description 00 00 00 855GME Hos...

Page 45: ...ilable for PCI 11 User Available for PCI 12 PS 2 mouse port 13 Reserved math coprocessor 14 Primary IDE 15 Secondary IDE Default but can be changed to another IRQ SMBUS Device Slave Address SIO 00101101b DIMM0 01010000b DIMM1 01010001b Clock Chip Write 11010010b Clock Chip Read 11010011b PCI Interrupt Routing Map PCI Device ID SEL PIRQA PIRQB PIRQC PIRQD PIRQE PIRQF PIRQG PIRQH PCI Riser AD18 INTA...

Page 46: ... following rows resume the counting on the same side of pin number 1 The counting is NOT circular like Integrated Circuits legacy from electronic tubes DB9 Female Front view DB9 Male Front view 5 4 3 2 1 9 8 7 6 1z2z3z4z5z 6z7z8z9z Header connectors are numbered alternately i e pin number 2 is in the other row but in the same column of pin number 1 Pin number 3 is in the same row of pin 1 but in t...

Page 47: ...rt COM3 6 Header J20 1 DCD3 2 DSR3 3 RX3 4 RTS3 5 TX3 6 CTS3 7 DTR3 8 RI3 9 GND 10 NC 11 DCD4 12 DSR4 13 RX4 14 RTS4 15 TX4 16 CTS4 17 DTR4 18 RI4 19 GND 20 NC 21 DCD5 22 DSR5 23 RX5 24 RTS5 25 TX5 26 CTS5 27 DTR5 28 RI5 29 GND 30 NC 31 DCD6 32 DSR6 33 RX6 34 RTS6 35 TX6 36 CTS6 37 DTR6 38 RI6 39 GND 40 NC 39 ...

Page 48: ...rted to 7 RX2 optional 1Gbe Table A 13 U14A Ethernet 2 RJ45 optional Pin Ethernet 2 optional 1Gbe Connector U14A 1 TX TX1 optional 1Gbe 2 TX TX1 optional 1Gbe 3 RX RX1 optional 1Gbe 4 Shorted to 5 TX2 optional 1Gbe 5 Shorted to 4 TX2 optional 1Gbe 6 RX RX1 optional 1Gbe 7 Shorted to 8 RX2 optional 1Gbe 8 Shorted to 7 RX2 optional 1Gbe Table A 14 J6 USB Ports 4 5 Header Connector Pin USB Header J6 ...

Page 49: ...Power Switch GND 9 5V 10 NC Table A 16 J32 Front Panel Header Connector IR Pin Front Panel IR Header J32 1 Infra Red Rx Opt 2 GND 3 GND 4 NC 5 Infra Red Tx Opt 6 5VDC Table A17 J17 Parallel Header Connector Pin Parallel Header J17 1 STROBE 2 AUTOFEED 3 DATA BIT 0 4 ERROR 5 DATA BIT 1 6 INIT 7 DATA BIT 2 8 SLCT IN 9 DATA BIT 3 10 GND 11 DATA BIT 4 12 GND 13 DATA BIT 5 14 GND 15 DATA BIT 6 16 GND 17...

Page 50: ...Sense Rear Chassis FAN J27 1 GND PWM 2 12V 3 Sense External Battery JP7 1 Vbat 2 GND Speaker Alternate J12 1 VCC 2 GND PWM 3 GND PWM Optional 12VDC Brick Connector J29 1 12VDC 2 GND 3 GND CD IN J9 1 Left 2 GND 3 GND 4 Right FLOPPY Power J31 1 12V 2 GND 3 GND 4 5V Table A 19 J5 LVDS Backlight Connector Pin LVDS Backlight J5 1 Inverter Vcc 2 GND 3 GND 4 Backlight Logic Vcc 5 SMBUS Clock optional 6 S...

Page 51: ...3V 4 LVDS DDC VCC 3 3V 5 NC 6 DDC CLK 7 DDC DATA 8 LVDS YAM0 9 LVDS YAP0 10 GND 11 LVDS YAM1 12 LVDS YAP1 13 GND 14 LVDS YAM2 15 LVDS YAP2 16 GND 17 LVDS CLK AM 18 LVDS CLK AP 19 GND 20 LVDS YBM0 21 LVDS YBP0 22 GND 23 LVDS YBM1 24 LVDS YBP1 25 GND 26 LVDS YBM2 27 LVDS YBP2 28 GND 29 LVDS CLK BM 30 LVDS CLK BP 43 ...

Page 52: ...Gator Mini ITX Installation Guide User s Notes 44 ...

Page 53: ...block initialization portion of the BIOS Checkpoint Code Description Before D1 Early chipset initialization is done Early super I O initialization is done including RTC and keyboard controller NMI is disabled D1 Perform keyboard controller BAT test Check if waking up from power management suspend state Save power on CPUID value in scratch CMOS D0 Go to flat mode with 4GB limit and GA20 enabled Ver...

Page 54: ...by the recovery file E0 Initialize the floppy controller in the super I O Some interrupt vectors are initialized DMA controller is initialized 8259 interrupt controller is initialized L1 cache is enabled E9 Set up floppy controller and data Attempt to read from floppy EA Enable ATAPI hardware Attempt to read from ARMD and ATAPI CDROM EB Disable ATAPI hardware Jump back to checkpoint E9 EF Read err...

Page 55: ... information setup key message and any OEM specific information 38 Initializes different devices through DIM See DIM Code Checkpoints section of document for more information 39 Initializes DMAC 1 DMAC 2 3A Initialize RTC date time 3B Test for total memory installed in the system Also Check for DEL or ESC keys to limit memory test Display total memory in the system 3C Mid POST initialization of ch...

Page 56: ...also reserved Function 2 searches for and initializes any PnP PCI or AGP video devices 38 Initialize different buses and perform the following functions Boot Input Device Initialization function 3 IPL Device Initialization function 4 General Device Initialization function 5 Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller Function 4 se...

Page 57: ...is running in ACPI mode AA System is running in APIC mode 01 02 03 04 05 Entering sleep state S1 S2 S3 S4 or S5 10 20 30 40 50 Waking from sleep state S1 S2 S3 S4 or S5 Critical Error BEEP Codes The following table describes the beep codes that are used by AMIBIOS Table B 6 AMIBIOS Beep Codes Number of Beeps Description 1 Memory refresh timer error 2 Parity error 3 Main memory read write test erro...

Page 58: ...Gator Mini ITX Installation Guide User s Notes 50 ...

Page 59: ... IEEE 802 3 Ethernet interface for 1000BASE T 100BASE_TX and 10BASE T applications 802 3 802 3u and 802 3ab The controller is capable of transmitting and receiving data at rates of 1000 Mbps 100 Mbps or 10 Mbps In addition to managing MAC and PHY layer functions the controller provides a 32 bit wide direct Peripheral Component Interconnect PCI 2 3 compliant interface capable of operating at 33 or ...

Page 60: ...tive load of less than 2500 pF This results in a line length of approximately 20 m The maximum slope of the signal is limited to 30 V ms The intention here is to limit any reflections that can occur to the rise and fall times of the signal Therefore transmission line theory does not need to be applied so no impedance matching and termination measures are necessary Do not connect termination resist...

Page 61: ...arios Electrical TIA EIA 422 ITU T V 11 is comparable to TIA EIA 485 It is limited to unidirectional data traffic and is terminated only at the line end opposite to the driver The maximum line length is 1200m the maximum data rate is determined by the signal rise and fall times at the receiver s side requirement 10 of bit duration TIA EIA 422 allows up to ten receivers input impedance of 4 kΩ atta...

Page 62: ... line termination to avoid line reflections allows very high data rates and a cable length of up to 1200 m Advantages of Differential Transmission Differential data transmission schemes are less susceptible to common mode noise than single ended schemes Because this kind of transmission uses two wires with opposite current and voltage swings compared to only one wire for single ended any external ...

Page 63: ...smission Please read the Differential Transmission explanation in the previous RS 422 section Termination Resistors Follow instructions in the previous RS 422 and RS 485 sections The termination resistors available are rated to 120Ω Ground Connections All 422 and 485 compliant system configurations shown up to this point do not have incorporated signal return paths to ground Obviously having a sol...

Page 64: ...Gator Mini ITX Installation Guide Watchdog Timer The Watchdog Timer WDT is optional 56 ...

Page 65: ...s set 3D pipeline states and control the processing functions The 2D instructions provide an efficient method for invoking BLT operations 3D Engine The 3D engine of the GMCH has been designed with a deeply pipelined architecture where performance is maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the same primitive The GMCH supports...

Page 66: ...nterface to support LVDS LCD panel resolutions up to UXGA The display pipe provides panel up scaling to fit a smaller source image onto a specific native panel size as well as provides panning and centering support The LVDS port is only supported on Pipe B The LVDS port can only be driven by Pipe B either independently or simultaneously with the Analog Display port Spread Spectrum Clocking is supp...

Page 67: ...he data The maximum pixel rate is increased to 224 MHz but may be limited to less than that due to restrictions elsewhere in the circuit The LVDS Port Enable bit enables or disables the entire LVDS interface When the port is disabled it will be in a low power state Once the port is enabled individual driver pairs will be disabled based on the operating mode Disabled drivers can be powered down for...

Page 68: ...rement is met Back Light Inverter Control The GMCH offers integrated PWM for TFT panel Backlight Inverter control Other methods of control are specified below SMBus based Backlight Brightness Control GMBus based Backlight Brightness Control PWM based Backlight Brightness Control DBL Display Brightness Link to VDL Video Data Link Power Sequencing Concurrent and Simultaneous Display The GMCH has two...

Page 69: ...Appendix D On Board Video User s Notes 61 ...

Page 70: ......

Page 71: ...MN GMEIX 01 ...

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