Contec PT-955SHX, User Manual

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6. Appendix
68
PT-955SxX User’s manual
POST Codes
Table 6.3. POST Codes < 1 / 3 >
POST
(hex)
Description
< Security (SEC) phase >
1h
Power on. Reset type detection (hard/soft)
2h
AP initialization before loading microcode
3h
North Bridge initialization before loading microcode
4h
South Bridge initialization before loading microcode
5h
OEM initialization before loading microcode
6h
Loading microcode
7h
AP initialization after loading microcode
8h
North Bridge initialization after loading microcode
9h
South Bridge initialization after loading microcode
Ah
OEM initialization after loading microcode
Bh
Cache initialization
< Pre-EFI Initialization (PEI) phase >
10h
PEI Core is started
11h
Pre-memory CPU initialization is started
12h – 14h
Pre-memory CPU initialization (CPU module specific)
15h
Pre-memory North Bridge initialization is started
16h – 18h
Pre-memory North Bridge initialization (North Bridge module specific)
19h
Pre-memory South Bridge initialization is started
1Ah – 1Ch
Pre-memory South Bridge initialization (South Bridge module specific)
1Dh – 2Ah
OEM pre-memory initialization codes
2Bh
Memory initialization: Serial Presence Detect (SPD) data loading
2Ch
Memory initialization: Memory detection
2Dh
Memory initialization: Programming memory timing information
2Eh
Memory initialization: Configuring memory
2Fh
Memory initialization: Other
30h
Reserved for ASL (see ACPI/ASL Checkpoints)
31h
Memory installed
32h
CPU post-memory initialization is started
33h
CPU post-memory initialization: Cache initialization
34h
CPU post-memory initialization: Application Processor(s) (AP) initialization
35h
CPU post-memory initialization: Boot Strap Processor (BSP) selection
37h
CPU post-memory initialization: System Management Mode (SMM) initialization
38h
Post-memory North Bridge initialization is started
39h – 3Ah
Post-memory North Bridge initialization (North Bridge module specific)
3Bh
Post-memory South Bridge initialization is started
3Ch – 3Eh
Post-memory South Bridge initialization (South Bridge module specific)
3Fh – 4Eh
OEM post-memory initialization codes
4Fh
DXE IPL is started
< Driver Execution Environment (DXE) phase >
60h
DXE Core is started
61h
NVRAM initialization
62h
South Bridge Runtime Services are installed
63h
CPU DXE installation is started
64h-67h
CPU DXE installation is started (CPU module specific)
68h
PCI Host Bridge is installed