3. External Connection
36
DIO-32DM3-PE
Eternal start signal (EXTSTART0/EXTSTART1)
These input signals start bus mastering with an external signal. The signal level is LVTTL and you
can select and enable the rising or falling edge with the software. In order to detect the signal edge, a
high- and low-level hold time of 25ns is needed at minimum.
tHIH : High level hold time 25ns (Min.)
tHIL : Low level hold time 25ns (Min.)
Figure 3.7. External start signal
External stop signal (EXTSTOP0/EXTSTOP1)
These input signals stop bus mastering with an external signal. The signal is LVTTL level and you can
select and enable the rising or falling edge with the software. In order to detect the signal edge, a high-
and low-level hold time of 50ns is needed at minimum.
Handshake Signal (EXTREQ0/EXTACK0/ EXTREQ1/EXTACK1)
These signals handshake with external devices. The signal is LVTTL level and controlled with
negative logic.
Input
tREQIL : EXTREQ0 low width 25ns (Min.)
tACKOL : EXTACK0 low width 100ns
tHSIN : Handshaking time 100ns (Min.)
Figure 3.8. Handshake Signals at the Time of Input
EXTSTART0
EXTSTSRT1
tHIH
tHIH
tHIL
EXTRAQ0 (In)
DATA (In)
EXTACK0 (Out)
tREQIL
Invalid
Valid
(1)
(2)
(3)
tHSIN
tACKOL
Summary of Contents for DIO-32DM3-PE
Page 7: ...vi DIO 32DM3 PE ...
Page 17: ...1 Before Using the Product 10 DIO 32DM3 PE ...
Page 35: ...2 Setup 28 DIO 32DM3 PE ...
Page 47: ...3 External Connection 40 DIO 32DM3 PE ...
Page 57: ...5 About Software 50 DIO 32DM3 PE ...
Page 62: ......