Connect Tech - Xtreme/Multi-I/O - Users Guide
Document: CTIM-00116
Revision: 0.02
0.02
Page 41 of 50
Connect Tech Inc. Proprietary Information
Date: Apr. 14, 2015
FPGA Configuration Registers
The “Configuration” registers are accessed via an SPI operation that either sets (writes) the contents of a register, or
retrieves (reads) its contents.
One 32 bit word is sent to the FPGA which controls the operation to be performed. It is encoded as follows…
Control Item
(Bit name)
Bit
Offset
Comment(s)
READ_WRITE
31
1= Read operation is performed
0= Write operation is performed
Not used
30
For possible future use
REG_ADDR
29
24 Address of the Configuration Register to be accessed
Not used
23
16 For possible future use
REG_DATA
15
0
Register Data
When the operation is Write, these bits must contain data
appropriate for the register being addressed.
When the operation is Read, these bits can be any value,
however zero is probably a good choice.
When the 32 bit word is sent to the FPGA, one 32 bit word is simultaneously received by the SPI port on the PIC32,
according to the following conditions…
When the operation is a Write, the value returned is:
o
equal to the sent word, with all bits inverted.
When the operation is a Read, the value returned has:
o
the upper 16 bits equal to the upper 16 bits of the sent word, inverted.
o
the lower 16 bits equal to the value of the register addressed.
This is the method by which the PIC32 can verify that the operation was “seen” by the FPGA.
