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Connect Tech - Xtreme/Multi-I/O - Users Guide

Document: CTIM-00116
Revision: 0.02

0.02

Page 32 of 50

Connect Tech Inc. Proprietary Information

Date: Apr. 14, 2015

of a “message” is deemed to have finished, any further data placed into the FIFO is treated as the “

next

”

message and will wait for the appropriate J1708 Bus Idle interval. The application software is notified by the
generation of the

TX Success

interrupt. This interrupt occurs just after the last bit of the last byte is sent (during

the STOP bit).

J1708 Interrupts

A variety of events are detected during the operation of the J1708 controller. These events are reported to the
software via interrupts. These interrupts are…



TX Success



TX Aborted



TX Problem



TX FIFO Almost Empty



TX FIFO Empty



RX FIFO Almost Full



RX FIFO Full



RX EOM

Details of these interrupts can be found in the section for the

J1708 Interrupt Status Register

.

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Summary of Contents for Multi-I/O

Page 1: ...uide Connect Tech Inc 42 Arrow Road Guelph ON CANADA N1K 1S6 Tel 519 836 1291 Toll Free 800 426 8979 North America Only Fax 519 836 4878 Email sales connecttech com Web www connecttech com CTIM 00116 Revision 0 02 Apr 14 2015 ...

Page 2: ...rd Address Decoding Capabilities 14 Command Groups 14 Serial Ports UARTS 15 Serial Ports Enable Disable 16 Serial Port Clocking 16 Serial Port DTR DSR Wrapback 16 RS422 485 Port 5 Settings 17 CAN Ports SJA1000 18 CAN Port Clocking 19 Board Configuration 19 J1708 Configuration 19 Misc Configuration 20 IO Address Ranges set with IOD command 20 Testing Debugging 20 Operation 21 MultiTech Modules 21 S...

Page 3: ...ption of Good Transmitted Bytes 34 TX Priority Register Offset 0x02 34 TX Problem Limit Register Offset 0x03 34 J1708 Interrupt Status Register Offset 0x04 35 FIFO Status Register Offset 0x05 35 RX EOM Level Register Offset 0x06 36 RX Almost Full Level Register Offset 0x07 36 User Ta Register Offset 0x08 37 Data FIFO s 37 J1708 IO 37 IO Connector Jumper Locations 38 Serial Port 8 to Module GPIO Co...

Page 4: ... to contact us directly Our technical support is always free Contact Information Mail Courier Connect Tech Inc Technical Support 42 Arrow Road Guelph ON Canada N1K 1S6 Email Internet sales connecttech com support connecttech com www connecttech com Note Please go to the Download Zone or the Knowledge Database in the Support Center on the Connect Tech Inc website for product manuals installation gu...

Page 5: ...hould the product prove to be irreparable Connect Tech Inc reserves the right to substitute an equivalent product if available or to retract lifetime warranty if no replacement is available The above warranty is the only warranty authorized by Connect Tech Inc Under no circumstances will Connect Tech Inc be liable in any way for any damages including any lost profits lost savings or other incident...

Page 6: ...116 Revision 0 02 0 02 Page 6 of 50 Connect Tech Inc Proprietary Information Date Apr 14 2015 Revision History Revsion Date Changes 0 01 June 11 2013 Original 0 02 Apr 14 2015 Add revise information in the Configuration section to clarify some important points ...

Page 7: ... functionality ESD Warning Electronic components and circuits are sensitive to ElectroStatic Discharge ESD When handling any circuit board assemblies including Connect Tech COM Express carrier assemblies it is recommended that ESD safety precautions be observed ESD safe best practices include but are not limited to Leaving circuit boards in their antistatic packaging until they are ready to be ins...

Page 8: ...TXT file which has been placed there when the unit was tested This file is a good starting point for any customer desired settings Copy this file to some other folder on your computer system Edit the copy and save it Delete the CONFIG TXT file from the folder on the Xtreme Multi I O board Copy the file back to the folder on the Xtreme Multi I O board This file is processed and the settings stored ...

Page 9: ...Connect Tech Xtreme Multi I O Users Guide Document CTIM 00116 Revision 0 02 0 02 Page 9 of 50 Connect Tech Inc Proprietary Information Date Apr 14 2015 ...

Page 10: ...age 10 of 50 Connect Tech Inc Proprietary Information Date Apr 14 2015 Typical CONFIG TXT file U1P 0x300 U2P 0x320 U1I 10 U2I 10 RS1 E RS2 E RS3 E RS4 E RS5 E RS6 E RS7 E RS8 E UPD Resulting ERRRORS TXT file U1P IO 0x0300 U2P IO 0x0320 U1I interrupt set to 10 U2I interrupt set to 10 ...

Page 11: ...ettings can be applied to other boards using the Configuration File Method described above NOTE Port settings like baud rate bits etc do not matter when configuring the board via the virtual serial port Setup commands are entered by typing them on the terminal application s used interface or by using the file sending or transfer facility of that application Each command is processed upon pressing ...

Page 12: ... Uart 7 is ENABLED Uart 8 is ENABLED Port 5 termination enable disable setting T Uart 1 DTR DSR wrapback is CONNECTED Uart 2 DTR DSR wrapback is CONNECTED Uart 3 DTR DSR wrapback is CONNECTED Uart 4 DTR DSR wrapback is CONNECTED Uart 5 DTR DSR wrapback is CONNECTED S1R Socket 1 RESET NO S2R Socket 2 RESET NO C1 CAN1 IO 0x0000 255 CAN1 is DISABLED C2 CAN2 IO 0x0000 255 CAN2 is DISABLED CM BASIC Por...

Page 13: ...qtalk minicom realterm etc to configure the port settings interactively This method is also applicable to situations where the application needs to change certain settings dynamically as part of the application s operation However the primary PC 104 Bus settings like IO Memory addresses or interrupts would not be candidates for any dynamic operations NOTE Because this method requires some settings...

Page 14: ...ds restrict the usable I O space to 0x3FF Board Address Decoding Capabilities All the ports Uart CAN J1708 of this board can be setup to reside in either IO or MEMORY space However in most situations the Uart Serial Ports will be setup in IO space due to software limitations and the CAN Ports in MEMORY space because the SJA1000 devices have too many registers to fit easily in IO space The J1708 Po...

Page 15: ...te 1 below n as above v Base Address value can be from See the IOD command for setting the IO decoding width and the resulting IO address range UnI v Set the IRQ for a group of Ports n as above v one of these possible IRQ selections 3 4 5 6 7 9 10 11 12 14 15 Notes 1 When the Address is entered as a single value ie U1P 0x300 then this is the Base Address for the group of Ports with each successive...

Page 16: ... from the Port 4 Isolated Line Transceiver therefore Port 4 must be Enabled to allow the LED outputs to operate properly 2 The connections between Serial Port 8 and the GPIO pins of Module Socket 2 are implemented with zero ohm resistors to select which GPIO pins to use see the Serial Port 8 to Module GPIO Configuration section for details Serial Port Clocking These commands allow 4 different cloc...

Page 17: ...r 14 2015 RS422 485 Port 5 Settings Command Operation Notes P5 Query the Port 5 mode of operation RSZ Query the Termination state of Port 5 P5 v Set the Port 5 mode of operation v F for Full Duplex H for Duplex J for J1708 mode RSZ v Set the Termination state of Port 5 v T to enable the Termination O to disable the Termination See note 1 below ...

Page 18: ...able the Port D to disable the Port Notes 1 When the Address is entered as a single value ie CP 0x400 then this is the Base Address for the group of Ports with the next Port being set Base 0x80 bytes However when the Addresses are entered as a comma separated list ie CP 0x400 0x500 then each Port is set to the Address value indicated Examples o With CM B CP 0x400 CAN Port 1 0x400 CAN Port 2 0x480 ...

Page 19: ...se commands allow the J1708 Port to be configured with Address and IRQ assignments The assignments can also be queried Command Operation Notes J Query the J1708 Base Address and IRQ settings JP Query the J1708 Base Address setting JI Query the J1708 IRQ setting JS Query the Enable Disable state of the J1708 Port JP v Set the J1708 Port Base Address v Base Address value See Note 1 below See the IOD...

Page 20: ...anges to Non Volatile storage IO Address Ranges set with IOD command The IO Address range depends on the IO Address decoding width IO Decode Width Base IO Address Range Uart Ports CAN Ports J1708 Port Board 10 0x000 to 0x3F8 0x000 to 0x3E0 Basic mode 0x000 to 0x380 Pelican mode 0x000 to 0x3E0 0x000 to 0x3FE 11 0x000 to 0x7F8 0x000 to 0x7E0 Basic mode 0x000 to 0x780 Pelican mode 0x000 to 0x7E0 0x00...

Page 21: ...ultitech wireless modules can be plugged into the top side of this board Each communicates through a serial port as described in the next section Refer to the IO Connector Jumper Locations section for the locations of the Sockets Each module can be powered by either 5V or 3 3V by installing jumpers in the appropriate locations Jumpers are installed in pairs as shown below PCB Locations ...

Page 22: ...board First Quad Uart o Four isolated RS232 interface o Port Order 1 Header P1 2 Header P2 3 Header P3 4 Header P4 Second Quad Uart o One isolated RS422 RS485 Port o Two ports connected to Module sockets P6 and P7 o One port connected to PIC32 for Command line based configuration changes o Port Order 1 RS422 RS485 to Header P5 2 MultiTech module P6 3 MultiTech module P7 4 To PIC32 Uart Registers R...

Page 23: ... These 4 serial ports connect to Header group P1to P4 as indicated in the sketch below as viewed from the edge of the board Each port can support bit rates up to 921 6K and has xxxx V 1 of isolation from each other and from the main circuits Pin Number Signal 1 N C 2 N C 3 RxD 4 RTS 5 TxD 6 CTS 7 N C 8 N C 9 GND Isolated 10 5V Isolated limited to 100 mA N C Not Connected ...

Page 24: ...8 Port is enabled by the JS command this isolated interface circuit is re commissioned for the J1708 port The IO header has special connection pins for the J1708 Port Pins 3 4 and 5 6 must be shorted so that the J1708 interface will operate properly Pin Number Signal 1 J1708 2 J1708 3 RX 4 TX 5 TX 6 RX 7 Slow Slew Rate enable strap to pin 9 8 Termination Enable strap to pin 10 9 GND Isolated 10 5V...

Page 25: ...ted from the other circuits on the board and are connected to IO headers P9 and P10 Each port can support bit rates up to 1M and has xxxx V 1 of isolation from each other and from the main circuits Both CAN controllers are clocked from the same source which can be setup to be either 16 MHz or 24 MHz Pin Number Signal 1 N C 2 GND Isolated 3 CAN 4 CAN 5 GND Isolated 6 CAN for termination strap 7 CAN...

Page 26: ...t CTIM 00116 Revision 0 02 0 02 Page 26 of 50 Connect Tech Inc Proprietary Information Date Apr 14 2015 CAN Port Registers Refer to the NXP SJA1000 data sheet for details of the CAN Controller registers A brief screenshot is shown here for convenience ...

Page 27: ...ch LED is current limited on the board to approximately 6 5 mA Pin Number Signal Primary Function Secondary Function 1 LED1 Link Activity from Module 1 P6 Software driven from register in FPGA 2 LED1 3 LED2 Link Activity from Module 2 P7 Software driven from register in FPGA 4 LED2 5 LED3 From GPIO pin 51 Module 2 P7 Software driven from register in FPGA 6 LED3 7 LED4 Uart ports operating at highe...

Page 28: ...interrupt is active CAN Port 1 2 0x4 CAN Port 1 interrupt is active CAN Port 2 3 0x8 CAN Port 2 interrupt is active J1708 Port 4 0x10 J1708 Port interrupt is active Unused 5 7 Reserved for future use RESET_CONT Register Offset 0x00 write only Software can use the Miscellaneous Control register to reset various circuits on the board Writing a 1 to the respective bit will hold the reset on the respe...

Page 29: ...olled by the LEDn_STATE bit See Note 1 below LED2_STATE 2 0x4 Same as above for LED2 LED2_ENAB 3 0x8 Same as above for LED2 LED3_STATE 4 0x10 Same as above for LED3 LED3_ENAB 5 0x20 Same as above for LED3 LED4_STATE 6 0x40 Same as above for LED4 LED4_ENAB 7 0x80 Same as above for LED4 Notes 1 The ENAB bit s allows software to take control the LED outputs 1 to 4 The primary function of the LED is i...

Page 30: ... will begin hunting for 19 consecutive Bus Idle periods During this time both the Receiver and Transmitter will not receive send any data bits Once 19 Idles are found the Receiver and Transmitter become operational Data bytes are framed in the usual asynchronous fashion ie 1 START bit 8 data bits 1 STOP bit When a legal START bit is detected the following data bits are shifted into the Receiver da...

Page 31: ... begin their bit transmissions at the same or nearly same point in time there is a variety of transmission issues that are detected and acted upon by the this J1708 controller The detection is possible because all transmitted bits are also received At each byte boundary the byte sent is compared to the byte received 1 In circumstances where there is heavy data traffic on the Bus there may be situa...

Page 32: ...n software is notified by the generation of the TX Success interrupt This interrupt occurs just after the last bit of the last byte is sent during the STOP bit J1708 Interrupts A variety of events are detected during the operation of the J1708 controller These events are reported to the software via interrupts These interrupts are TX Success TX Aborted TX Problem TX FIFO Almost Empty TX FIFO Empty...

Page 33: ... one 1 is written to the appropriate bit does the indicated action take place Writing a zero 0 to a bit has NO effect All bits in this register will self clear when the operation takes place Control Item Bit Offset Bit Value Comment s Restart J1708 Bus SYNC 0 0x1 Bit clears when the Receiver enters the SYNC state Abort TX 1 0x2 Bit clears when Abort is completed TX Kick 2 0x4 Force the generation ...

Page 34: ...or details about the meaning of Priority This setting controls how long the J1708 Bus must be Idle before a transmitted message can begin This Idle period is measured in Bit Intervals Control Item Bit Offset Comment s TX Priority Value 0 2 Values of 0 to 7 represent the 8 priority levels with 0 being the highest priority Default value is 7 lowest priority Unused 3 7 Not used Each priority value tr...

Page 35: ...Almost Full Level Register Remaining FIFO space is 512 N where N is defined by the RX Almost Full Level Register RX FIFO Full 6 0x40 Receiver FIFO is Full not a desirable situation RX EOM 7 0x80 Receiver EOM detected FIFO Status Register Offset 0x05 The Transmitter and Receiver FIFO s have signals that indicate the state of the respective FIFO these can be accessed through this read only register ...

Page 36: ...count reaches the threshold set in this register the RX FIFO Almost Full interrupt is generated This allows software to empty the data FIFO periodically during the reception of a message Control Item Bit Offset Comment s RX Almost Full Level value 0 4 Values of 1 to 31 Writing a value of zero will be ignored and the current value will be retained Default value is 16 Unused 5 7 Not used Software Im...

Page 37: ...as soon as data is placed in the data FIFO which can cause a collision with data being transmitted by some other device This feature is mainly useful for testing scenarios When this condition exists the Ignore Ta bit in the Control register will read as a one 1 To place the transmitter back into its normal priority derived delay mode the TX Priority register value must be written with an appropria...

Page 38: ...Connect Tech Xtreme Multi I O Users Guide Document CTIM 00116 Revision 0 02 0 02 Page 38 of 50 Connect Tech Inc Proprietary Information Date Apr 14 2015 IO Connector Jumper Locations ...

Page 39: ...esistors to 3 of the GPIO pins on the Socket module as indicated here Signal GPIO 0 GPIO 1 GPIO 2 TXD R82 R80 R78 RXD R83 R81 R79 The appropriate resistors need to be installed to connect the 2 serial signals to appropriate GPIO pins on the socket module Only 2 resistors should be installed one for each serial signal Do NOT install resistors so that both signals go to the same GPIO It is best to c...

Page 40: ...c is supplied by the PIC32 For setup purposes these registers can be queried with the SPIR command see the Testing Debugging section for a description of this command Configuration Enhancements Relative to a competitor s product our product offers configurations enhancements in these areas Any Port can be IO or Memory Space mapped Memory mapping extends to the full PC 104 Bus addressing range 24 b...

Page 41: ...uration Register to be accessed Not used 23 16 For possible future use REG_DATA 15 0 Register Data When the operation is Write these bits must contain data appropriate for the register being addressed When the operation is Read these bits can be any value however zero is probably a good choice When the 32 bit word is sent to the FPGA one 32 bit word is simultaneously received by the SPI port on th...

Page 42: ...2 2 PORT_CONFIG 2 Mem IO Configuration for Uart Port 3 RS232 3 PORT_CONFIG 3 Mem IO Configuration for Uart Port 4 RS232 4 PORT_CONFIG 4 Mem IO Configuration for Uart Port 5 RS422 485 J1708 5 PORT_CONFIG 5 Mem IO Configuration for Uart Port 6 MultiTech Module 1 6 PORT_CONFIG 6 Mem IO Configuration for Uart Port 7 MultiTech Module 2 7 PORT_CONFIG 7 Mem IO Configuration for Uart Port 8 PIC32 Serial C...

Page 43: ...0x318 o P5 0x320 o P6 0x328 o P7 0x330 o P8 0x338 Both CAN Ports disabled but with the following MEMORY address assignments o P9 0x0D0000 o P10 0x0D0080 J1708 Port disabled but with the following MEMORY address assignment o P11 0x0D0200 Control Item Bit Offset Comment s PORT_ENAB 15 1 Enabled 0 Disabled When a Port is enabled its Base Address is decoded and its interrupt is enabled MEM_IO 14 Memor...

Page 44: ...dth when operated in Basic mode The choice of CAN Port decoding width is in the MEM_CONFIG register o J1708 Port decodes a 32 byte width ADDR_SEL Bit PC 104 Address Bit Number IO Mode Conditions for decoding MEM Mode Conditions 8 11 All Ports when IO decoding of Bit 11 is enabled 15 All Ports 7 10 All Ports when IO decoding of Bit 10 is enabled 14 All Ports 6 9 All Ports 13 All Ports 5 8 All Ports...

Page 45: ...ADDR_SEL 10 0 Address selection bits These bits are compared to PC 104 address bits to select the Port during read or write accesses on the PC 104 bus The bits are compared according to the table below 1 1 2 1 Address Bit Comparisons Address Selection bits from the BOARD_CONFIG register are compared to PC 104 Bus address bits in order to select the Board Control registers according to the followin...

Page 46: ...RQ 11 J1708 Port on IRQ 15 Control Item Bit Offset Bit Value Comment s Not Used 15 11 IRQ15 10 0x400 Use IRQ15 IRQ14 9 0x200 Use IRQ14 IRQ12 8 0x100 Use IRQ12 IRQ11 7 0x80 Use IRQ11 IRQ10 6 0x40 Use IRQ10 IRQ9 5 0x20 Use IRQ9 IRQ7 4 0x10 Use IRQ7 IRQ6 3 0x8 Use IRQ6 IRQ5 2 0x4 Use IRQ5 IRQ4 1 0x2 Use IRQ4 IRQ3 0 0x1 Use IRQ3 Important Notes Multiple Ports can be assigned to any IRQ but any Port ca...

Page 47: ... IO Space Set either bit to 1 to enable the respective address bit to be included in the decoding Bit 11 enables the decoding of PC 104 address bit 11 This bit must not be set with bit 10 reset Bit 10 enables the decoding of PC 104 address bit 10 Not used 9 CAN_PEL 8 Enable Pelican mode decoding for the CAN Ports when using IO space decoding MEM_REGION 7 0 Address selection bits These bits are com...

Page 48: ... 0 02 Page 48 of 50 Connect Tech Inc Proprietary Information Date Apr 14 2015 1 1 2 2 1 Common Memory Locations Memory Address PC 104 Address Bit MEM_REGION value 23 22 21 20 19 18 17 16 0x0C0000 0 0 0 0 1 1 0 0 0x0C 0x0D0000 0 0 0 0 1 1 0 1 0x0D 0xF90000 1 1 1 1 1 0 0 1 0xF9 ...

Page 49: ...IC32_RST 13 1 PIC32 Reset applied 0 Reset released Reset of the PIC32 can also be activated via the Board Control register MOD_RST 12 11 0 Module Reset applied 1 Reset released Bit 12 Module 1 Uart Port 6 Bit 11 Module 2 Uart Port 7 Reset of the Modules can also be activated via the Board Control register P5_HD 10 1 Port 5 operated in RD485 Half duplex mode P5_RX_ONLY 9 1 Port 5 operated in Receiv...

Page 50: ...0 Connect Tech Inc Proprietary Information Date Apr 14 2015 FPGA_VERSION Reg 19 This is a read only register that provides version information Control Item Bit Offset Comment s Not Used 15 8 Ignored on a Write Read as zero s VER 7 0 Version letter ASCII value of a alphabetic character A B C etc ...

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