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TCEDm11
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Table 31 IRQ Lines in APIC mode
IRQ#
Available Typical Interrupt Source
Connected to Pin / Function
0
No
Counter 0
Not applicable
1
No
Keyboard
Not applicable
2
No
Cascade Interrupt from Slave PIC Not applicable
3
Yes
IRQ3 via SERIRQ
4
Yes
IRQ4 via SERIRQ
5
Yes
IRQ5 via SERIRQ
6
Yes
IRQ6 via SERIRQ
7
No
Reserved for BIOS purposes
8
No
Real-time Clock
Not applicable
9
No
SCI
SCI
10
Yes
IRQ10 via SERIRQ
11
Yes
IRQ11 via SERIRQ
12
Yes
IRQ12 via SERIRQ
13
No
Math processor
Not applicable
14
Yes
15
Yes
16
No
PIRQA, Integrated VGA Controller, UHCI Controller #3, PCI Express Root Port 0, PCI Express Port 0, PCI Express
Port 1, PCI Express Port 3
17
No
PIRQB, PCI Express Root Port 0, PCI Express Port 0, PCI Express Port 1, PCI Express Port 3
18
No
PIRQC, UHCI Controller #2, PCI Express Root Port 0, PCI Express Port 0, PCI Express Port 1, PCI Express Port 3,
Jmicron PATA Controller
19
No
PIRQD, PCI Express Root Port 0, PCI Express Port 0, PCI Express Port 1, PCI Express Port 3, SMBUS Controller,
UHCI Controller #1
20
Yes
PIRQE, onboard Gigabit LAN Controller, COMx Slot #0, COMx Slot #1, COMx Slot #2, COMx Slot #3
21
Yes
PIRQF, COMx Slot #0, COMx Slot #1, COMx Slot #2, COMx Slot #3
22
Yes
PIRQG, Intel High Definition Audio Controller, COMx Slot #0, COMx Slot #1, COMx Slot #2, COMx Slot #3
23
Yes
PIRQH, EHCI Host Controller #1, UHCI Controller #0, COMx Slot #0, COMx Slot #1, COMx Slot #2, COMx Slot #3
Note
In APIC mode, the PCI bus interrupt lines are connected with IRQ 16, 17, 18 and 19.
