Congatec 046901 User Manual Download Page 80

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2013

congatec

TU87m10

80/108

Feature

Options

Description

Maximum Read Request

Auto

128 Bytes

256 Bytes

512 Bytes

1024 Bytes

2048 Bytes

4096 Bytes

Set maximum read request size of PCI Express devices or allow system BIOS to select the value.

ASPM

Disabled

Auto

Force L0s

PCI Express Active State Power Management settings.

Extended Synch

Disabled

Enabled

If enabled, the generation of extended PCI Express synchronization patterns is allowed.

Link Training Retry

Disabled, 2, 3,

Defines number of retry attempts software will take to retrain the link if previous training attempt was unsuccessful.

Link Training Timeout (us)

10-10000

Default : 100

Defines number of microseconds software will wait before polling link training bit in the link status register. Value

ranges from 10 to 10000 us.

Unpopulated Links

Keep Link On

Disabled

In order to save power, software will disable unpopulated PCI Express links, if this option is set to disabled.

Restore PCIe Registers

Enabled

Disabled

On non-PCI Express aware operating systems some devices may not be re-initialized correctly after S3. Setting this

node to Enabled restores PCI Express configuration on S3 resume.

Warning: Enabling this may cause issues with other hardware after S3 resume.

10.4.5.2 PIRQ Routing & IRQ Reservation Submenu

Feature

Options

Description

PIRQA

Auto

, IRQ3, IRQ4,

IRQ5, IRQ6,

IRQ10, IRQ11,

IRQ14, IRQ15

Set interrupt for selected PIRQ. Please refer to the board’s resource list for a detailed list of devices connected to the

respective PIRQ.

NOTE: These settings will only be effective while operating in PIC (non-IOAPIC) interrupt mode.

PIRQB

same as PIRQA

PIRQC

same as PIRQA

PIRQD

same as PIRQA

PIRQE

same as PIRQA

PIRQF

same as PIRQA

PIRQG

same as PIRQA

PIRQH

same as PIRQA

Reserve Legacy Interrupt 1

None

, IRQ3,

IRQ4, IRQ5, IRQ6,

IRQ10, IRQ11,

IRQ14, IRQ15

The interrupt reserved here will not be assigned to any PCI or PCI Express device and thus maybe available for some

legacy bus device.

Reserve Legacy Interrupt 2 same as Reserve

Legacy Interrupt 1

same as Reserve Legacy Interrupt 1

Summary of Contents for 046901

Page 1: ...Copyright 2013 congatec AG TU87m10 1 108 COM Express conga TC87 4th Generation Intel Core i7 i5 i3 and Mobile Intel Celeron Single Chip Ultra Low TDP Processors User s Guide Revision 1 0...

Page 2: ...Preliminary release 1 0 2014 03 27 AEM Updated section 2 5 Power Consumption Updated section 3 Block Diagram Corrected the name of the congatec board controller in section 5 1 6 I2C Bus Fast Mode Cor...

Page 3: ...r indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user s guide In no event shall congatec AG be liable for any inci...

Page 4: ...n that should be observed Terminology Term Description GB Gigabyte 1 073 741 824 bytes GHz Gigahertz one billion hertz kB Kilobyte 1024 bytes MB Megabyte 1 048 576 bytes Mbit Megabit 1 048 576 bits kH...

Page 5: ...on specifications will be repaired or exchanged at congatec s option and expense Customer will obtain a Return Material Authorization RMA number from congatec AG prior to returning the non conforming...

Page 6: ...nical support for our customers so that our products can be easily used and implemented We request that you first visit our website at www congatec com for the latest documentation utilities and drive...

Page 7: ...4 5 1 9 Graphics Output VGA CRT 24 5 1 10 LCD LVDS eDP 25 5 1 11 General Purpose Serial Interface 25 5 1 12 Power Control 26 5 1 13 Power Management 29 5 2 Secondary Connector Rows C and D 30 5 2 1 PC...

Page 8: ...3 PCI Express Port Submenu 81 10 4 6 ACPI Submenu 82 10 4 7 RTC Wake Submenu 83 10 4 8 Trusted Computing Submenu 84 10 4 9 CPU Submenu 84 10 4 10 SATA Submenu 88 10 4 10 1 Software Feature Mask Confi...

Page 9: ...ash Interface Signal Descriptions 50 Table 15 Miscellaneous Signal Descriptions 51 Table 16 General Purpose I O Signal Descriptions 51 Table 17 Power and System Management Signal Descriptions 52 Table...

Page 10: ...table data throughput The COM computer on module integrates all the core components and is mounted onto an application specific carrier board COM modules are legacy free design no Super I O PS 2 keybo...

Page 11: ...n this user s guide are available on your particular module conga TC87 Part No 046901 046902 046903 046904 Processor Intel Core i7 4650U 1 7 GHz Dual Core Intel Core i5 4300U 1 9 GHz Dual Core Intel C...

Page 12: ...ansmitter Supports Single channel LVDS interface 1 x 18 bpp or 1 x 24 bpp Dual channel LVDS interface 2 x 18 bpp or 2 x 24 bpp panel VESA LVDS color mappings Automatic Panel Detection via Embedded Pan...

Page 13: ...7 supports the following operating systems Microsoft Windows 8 Microsoft Windows 7 Microsoft Windows Embedded Standard Linux 2 3 Mechanical Dimensions 95 0 mm x 95 0 mm 3 74 x 3 74 Height approximatel...

Page 14: ...Input Range Volts Derated Input Volts Max Input Ripple 10Hz to 20MHz mV Max Module Input Power w derated input Watts Assumed Conversion Efficiency Max Load Power Watts VCC_12V 12 12 11 4 12 6 11 4 10...

Page 15: ...ndows 7 Professional 64Bit Hyper Threading enabled Speed Step enabled CPU Turbo Mode enabled and Power Plan set to Power Saver This setting ensures that Core processors run in LFM lowest frequency mod...

Page 16: ...12 0 W 12V 100 Workload turbo mode enabled 2 30 A 27 6 W 12V 100 CPU and GPU workload turbo mode disabled 1 59 A 19 1 W 12V 100 CPU and GPU workload turbo mode enabled 2 41 A 28 9 W 12V Peak Power Con...

Page 17: ...rbo mode disabled 1 52 A 18 2 W 12V 100 CPU and GPU workload turbo mode enabled N A Peak Power Consumption 1 67 A 20 0 W 12V 2 5 4 Intel Celeron 2980U 1 6 GHz Dual Core 2MB Cache conga TC87 Art No 046...

Page 18: ...ecifications Temperature Operation 0 to 60 C Storage 20 to 80 C Humidity Operation 10 to 90 Storage 5 to 95 Caution The above operating temperatures must be strictly adhered to at all times When using...

Page 19: ...ect PCIe0 PCIe1 PCIe2 PCIe3 PCIe5 L0 PCIe5 L1 PCIe5 L2 eDP to LVDS Bridge HUB congatec System Management Controller X X X X X X PCIe5 L3 X X X X X X 2x SO DIMM X1 X2 SPI Flash 0 SPI Flash 1 LVDS eDP V...

Page 20: ...that the heatspreader is attached directly to the systems chassis thereby using the whole chassis as a heat dissipater For additional information about the conga TC87 heatspreader refer to section 4...

Page 21: ...eatspreader screws is 0 3 Nm Mechanical system assembly mounting shall follow the valid DIN IS0 specifications Caution When using the heatspreader in a high shock and or vibration environment congatec...

Page 22: ...s of rows C and D In this view the connectors are seen through the module top view C D A B A B 4 PCI Express Lanes 4x Serial ATA 8x USB 2 0 High Definition Audio I F Gigabit Ethernet connected via a x...

Page 23: ...A B connector The EHCI host controller in the PCH supports these interfaces with high speed full speed and low speed USB signalling The controller complies with USB standard 1 1 and 2 0 For more info...

Page 24: ...ti master I C Bus that has maximum I C bandwidth 5 1 7 PCI Express The conga TC87 offers 5 PCI Express lanes via the Intel 8 Series PCH LP Four of these lanes are offered externally on the A B connect...

Page 25: ...ther LVDS or eDP signals Both signals are not supported simultaneously 5 1 11 General Purpose Serial Interface Two TTL compatible two wire ports are available on Type 6 COM Express modules These pins...

Page 26: ...board hardware must drive this signal low until all power rails and clocks are stable Releasing PWR_OK too early or not driving it low at all can cause numerous boot up problems It is a good design p...

Page 27: ...he above shown voltage divider circuitry and the transistor stage the voltage measured at the PWR_OK input pin may be only around 0 8V when the 12V is applied to the module Actively driving PWR_OK hig...

Page 28: ...a result of modifications made in BIOS settings or by system software Power Supply Implementation Guidelines 12 volt input power is the sole operational power source for the conga TC87 The remaining n...

Page 29: ...The Deep Sx is a lower power state employed to minimize the power consumption while in S3 S4 S5 In the Deep Sx state the system entry condition determines if the system context is maintained or not A...

Page 30: ...ntegrated digital display interfaces such as HDMI and DisplayPort The conga TC87 offers the Digital Display Interface on the CD connector and supports up to three independent displays The display comb...

Page 31: ...igital Display Interface of the COM Express connector Note The conga TC87 supports a maximum of 2 independent DVI displays Revisions equipped with optional VGA interface support only 1 DVI interface S...

Page 32: ...the CD connector These ports are controlled by an xHCI host controller provided by the Intel 8 Series PCH LP integrated in the MCP The host controller allows data transfers of up to 5 Gb s and suppor...

Page 33: ...onga TC87 is equipped with a multi stage watchdog solution that is triggered by software The COM Express Specification does not provide support for external hardware triggering of the Watchdog which m...

Page 34: ...e their own CMOS default configuration and BIOS logo splash screen within the BIOS flash device Customized BIOS development by congatec for these changes is no longer necessary because customers can e...

Page 35: ...sily integrate all these features into their code The CGOS API congatec Operating System Application Programming Interface is the congatec proprietary API that is available for all commonly used Opera...

Page 36: ...ncludes coprocessors to calculate efficient hash and RSA algorithms with key lengths up to 2 048 bits as well as a real random number generator Security sensitive applications like gaming and e commer...

Page 37: ...ting AHCI may take advantage of performance features such as port independent DMA engines each device is treated as a master and hardware assisted native command queuing AHCI also provides usability e...

Page 38: ...f active cores The amount of time the processor spends in the Intel Turbo Boost 2 Technology state depends on the workload and operating environment Any of the following can set the upper limit of Int...

Page 39: ...about this subject THERMTRIP signal is used by Intel s Core i7 i5 i3 and Celeron processors for catastrophic thermal protection If the processor s silicon reaches a temperature of approximately 125 C...

Page 40: ...ntel 64 are not utilized 2 Compatibility Mode 64 bit operating system and 32 bit applications This mode requires all device drivers to be 64 bit The operating system will see the 64 bit extensions but...

Page 41: ...ing physical platform resources sharing them between multiple guest operating systems Intel VT is already incorporated into most commercial and open source VMMs including those from VMware Microsoft X...

Page 42: ...dby mode is set to S3 USB hardware must be powered by standby power source Set USB Device Wakeup from S3 S4 to ENABLED in the ACPI setup menu if setup node is available in BIOS setup program In Device...

Page 43: ...the RMH is multiplexed with Port 1 of the EHCI controller and is able to bypass the RMH for use as the Debug Port The hub operates like any USB 2 0 Discrete Hub and will consume one tier of hubs allow...

Page 44: ...nted by the chip vendors only pull ups or pull downs implemented by congatec are listed For information about the internal pull ups or pull downs implemented by the chip vendors refer to the respectiv...

Page 45: ...Audio Serial Data In 0 These signals are serial TDM data inputs from the three codecs The serial input is single pumped for a bit rate of 24 Mb s for Intel High Definition Audio I 3 3VSB AC 97 codecs...

Page 46: ...al ATA channel 0 Receive Input differential pair I SATA Supports Serial ATA specification Revision 3 0 SATA0_TX SATA0_TX A16 A17 Serial ATA channel 0 Transmit Output differential pair O SATA Supports...

Page 47: ...RX3 PCIE_RX3 B58 B59 PCI Express channel 3 Receive Input differential pair I PCIE Supports PCI Express Base Specification Revision 2 0 PCIE_TX3 PCIE_TX3 A58 A59 PCI Express channel 3 Transmit Output d...

Page 48: ...USB 2 0 compliant Backwards compatible to USB 1 1 USB5 B39 USB Port 5 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB6 A37 USB Port 6 data or D I O USB 2 0 compliant Backwards com...

Page 49: ...bilities I O OD 5V PU 1k2 3 3V Optional on rev C x and later VGA_I2C_DAT B96 DDC data line I O OD 5V PU 1k2 3 3V Optional on rev C x and later Table 12 LVDS Signal Descriptions Signal Pin Description...

Page 50: ...yer I 3 3V Table 14 SPI BIOS Flash Interface Signal Descriptions Signal Pin Description I O PU PD Comment SPI_CS B97 Chip select for Carrier Board SPI BIOS Flash O 3 3VSB Carrier shall pull to SPI_POW...

Page 51: ...gnal Pin Description I O PU PD Comment GPO0 A93 General purpose output pins Shared with SD_CLK Output from COM Express input to SD O 3 3V SDIO interface is not supported on the conga TC87 GPO1 B54 Gen...

Page 52: ...PCI Express wake up signal I 3 3VSB PU 1k 3 3VSB WAKE1 B67 General purpose wake up signal May be used to implement wake up on PS 2 keyboard or mouse activity I 3 3VSB PU 10k 3 3VSB BATLOW A27 Battery...

Page 53: ...BY is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend functions May be left unconnected if these functions are not used in the system design P VCC...

Page 54: ..._TX A72 eDP_TX2 LVDS_A0 B72 LVDS_B0 A18 SUS_S4 B18 SUS_STAT A73 eDP_TX1 LVDS_A1 B73 LVDS_B1 A19 SATA0_RX B19 SATA1_RX A74 eDP_TX1 LVDS_A1 B74 LVDS_B1 A20 SATA0_RX B20 SATA1_RX A75 eDP_TX0 LVDS_A2 B75...

Page 55: ...00 GND FIXED B100 GND FIXED A46 USB0 B46 USB1 A101 SER1_TX B101 FAN_PWMOUT A47 VCC_RTC B47 EXCD1_PERST A102 SER1_RX B102 FAN_TACHIN A48 EXCD0_PERST B48 EXCD1_CPPE A103 LID B103 SLEEP A49 EXCD0_CPPE B4...

Page 56: ...the Superspeed USB data path I USB_SSRX0 C3 I USB_SSTX0 D4 Additional transmit signal differential pairs for the Superspeed USB data path O USB_SSTX0 D3 O USB_SSRX1 C7 Additional receive signal diffe...

Page 57: ..._RX7 PEG_RX8 PEG_RX8 PEG_RX9 PEG_RX9 PEG_RX10 PEG_RX10 PEG_RX11 PEG_RX11 PEG_RX12 PEG_RX12 PEG_RX13 PEG_RX13 PEG_RX14 PEG_RX14 PEG_RX15 PEG_RX15 C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C69 C71 C72...

Page 58: ...G_TX15 D52 D53 D55 D56 D58 D59 D61 D62 D65 D66 D68 D69 D71 D72 D74 D75 D78 D79 D81 D82 D85 D86 D88 D89 D91 D92 D94 D95 D98 D99 D101 D102 PCI Express Graphics Transmit Output differential pairs Note Ca...

Page 59: ...TA if DDI1_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V PU 100k 3 3V DDI1_CTRLDATA_AUX is a boot strap signal see not below DDI enable strap already populated DDI1_DDC_AUX_SEL D34 Selects the funct...

Page 60: ...h DP3_AUX and HDMI3_CTRLCLK DP AUX function if DDI3_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V Not supported DDI3_CTRLDATA_AUX C37 Multiplex...

Page 61: ...with DDI2_PAIR2 and DDI2_PAIR2 O PCIE TMDS2_DATA1 TMDS2_DATA1 D42 D43 HDMI DVI TMDS differential pair Multiplexed with DDI2_PAIR1 and DDI2_PAIR1 O PCIE TMDS2_DATA2 TMDS2_DATA2 D39 D40 HDMI DVI TMDS di...

Page 62: ...ort of isochronous streams and secondary data Multiplexed with DDI1_PAIR0 and DDI1_PAIR0 O PCIE DP1_HPD C24 Detection of Hot Plug Unplug and notification of the link layer Multiplexed with DDI1_HPD I...

Page 63: ...ondary data Multiplexed with DDI3_PAIR2 and DDI3_PAIR2 O PCIE Not supported DP3_LANE1 DP3_LANE1 C42 C43 Uni directional main link for the transport of isochronous streams and secondary data Multiplexe...

Page 64: ...d logic may also implement a fault indicator such as an LED TYPE10 A97 Dual use pin Indicates to the carrier board that a Type 10 module is installed Indicates to the carrier that a Rev 1 0 2 0 module...

Page 65: ...71 PEG_RX6 D71 PEG_TX6 C17 RSVD D17 RSVD C72 PEG_RX6 D72 PEG_TX6 C18 RSVD D18 RSVD C73 GND D73 GND C19 PCIE_RX6 D19 PCIE_TX6 C74 PEG_RX7 D74 PEG_TX7 C20 PCIE_RX6 D20 PCIE_TX6 C75 PEG_RX7 D75 PEG_TX7 C...

Page 66: ...D45 RSVD C100 GND FIXED D100 GND FIXED C46 DDI3_PAIR2 D46 DDI2_PAIR2 C101 PEG_RX15 D101 PEG_TX15 C47 DDI3_PAIR2 D47 DDI2_PAIR2 C102 PEG_RX15 D102 PEG_TX15 C48 RSVD D48 RSVD C103 GND D103 GND C49 DDI3...

Page 67: ...O PCIE I O OD 3 3V PU100k 3 3V DDI1_CTRLDATA_AUX is a boot strap signal see not below DDI2_CTRLDATA_AUX DP2_AUX HDM2_CTRLDATA C33 Multiplexed with DP2_AUX and HDMI2_CTRLDATA DP AUX function if DDI2_DD...

Page 68: ...les that are not positively decoded are forwarded to the internal PCI Bus not the LPC Bus Only specified I O ranges are forwarded to the LPC Bus In the congatec Embedded BIOS the following I O address...

Page 69: ...e2 1Ch 02h PCI Express Root Port 2 00h Note2 1Ch 03h PCI Express Root Port 3 00h 1Dh 00h EHCI Host Controller 00h 1Fh 00h PCI to LPC Bridge 00h 1Fh 02h Serial ATA Controller 00h 1Fh 03h SMBus Host Con...

Page 70: ...1 These interrupt lines are virtual message based 2 Interrupt used by single function PCI Express devices INTA 3 Interrupt used by multifunction PCI Express devices INTB 4 Interrupt used by multifunct...

Page 71: ...device that should be used or an option to enter the BIOS setup program 10 2 Setup Menu and Navigation The congatec BIOS setup screen is composed of the menu bar left frame and right frame The menu ba...

Page 72: ...and time You can always return to the main setup screen by selecting the Main tab Feature Options Description Main BIOS Version no option Displays the main BIOS version OEM BIOS Version no option Disp...

Page 73: ...on Displays the processor microcode revision IGD HW Version no option Displays the version of the graphics controller IGD VBIOS Version no option Displays the video BIOS version Total Memory no option...

Page 74: ...y be used by the Internal Graphics Device Memory above the fixed graphics memory will be dynamically allocated by the graphics driver according to DVMT 5 0 specification MAX Use as much graphics memor...

Page 75: ...ecifies the congatec internal number of the respective panel data set Note Customized EDID utilizes an OEM defined EDID data set stored in the BIOS flash device Backlight Inverter Type None PWM I2C Se...

Page 76: ...lect the timeout value for the POST watchdog The watchdog is only active during the power on self test of the system and provides a facility to prevent errors during boot up by performing a reset Stop...

Page 77: ...ut 3 see above Selects the timeout value for the third stage watchdog event Watchdog ACPI Event Shutdown Restart Select the operating system event that is initiated by the watchdog ACPI event These op...

Page 78: ...rt initial baudrate 10 4 4 Hardware Health Monitoring Submenu Feature Options Description CPU Temperature no option Displays the actual CPU Temperature in C CPU Fan Speed no option Displays the actual...

Page 79: ...nable or disable PCI Express subtractive decode PCI Express Port 0 submenu Opens the PCI Express Port submenu PCI Express Port 1 submenu Opens the PCI Express Port submenu PCI Express Port 2 submenu O...

Page 80: ...led Disabled On non PCI Express aware operating systems some devices may not be re initialized correctly after S3 Setting this node to Enabled restores PCI Express configuration on S3 resume Warning E...

Page 81: ...etion Timeout timer SEFE Disabled Enabled Enable or disable Root PCI Express System Error on Fatal Error SENFE Disabled Enabled Enable or disable Root PCI Express System Error on Non Fatal Error SECE...

Page 82: ...Manual Auto No Snoop latency override for PCH PCIe No Snoop Latency Multiplier 1 ns 32 ns 1024 ns 32768 ns 1048576 ns 33554432 ns No Snoop latency multiplier for PCH PCIe No Snoop Latency Value 0 252...

Page 83: ...and OS polls for command completion Active Trip Point Disabled 15 C 23 C 31 C 39 C 47 C 55 C 63 C 71 C 79 C 87 C 95 C 103 C 111 C 119 C Specifies the temperature threshold at which the ACPI aware OS...

Page 84: ...d Processor Cores no option Displays the number of the Processor Cores Intel HT Technology no option Displays whether Intel HT Technology is supported Intel VT x Technology no option Displays whether...

Page 85: ...Prefetcher Disabled Enabled Enable or disable the Mid Level Cache L2 streamer prefetcher Adjacent Cache Line Prefetch Disabled Enabled Enable or disable the Mid Level Cache L2 prefetching of adjacent...

Page 86: ...ocks VR current value from further writes until a reset VR Current Value 0 8191 Default 0 Voltage regulator current limit 0 means automatic CPU C States Disabled Enabled Enable or disable CPU C states...

Page 87: ...ACPI CTDP BIOS Disabled Enabled Enable or disable ACPI CTDP BIOS support Configurable TDP Level TDP NOMINAL TDP DOWN TDP UP Disabled Allow reconfiguration of TDP levels base on current power and ther...

Page 88: ...rial ATA Port 0 1 2 3 no option Displays the name of the connected Hard Disk or DVDROM when the port is enabled Empty is displayed when the port is disabled or when the port is enabled but nothing is...

Page 89: ...T volumes can span internal and external SATA eSATA drives If disabled then any RAID volume can span internal and eSATA drives Intel Smart Response Technology Disabled Enabled Enable or disable Intel...

Page 90: ...ptical or hard disk drives SATA Port 0 Disk drive name Acoustic Mode Bypass Quiet Max Performance Acoustic noise level and performance optimization of optical or hard disk drives Bypass Use drive s pr...

Page 91: ...bled Enabled Enable or disable EHCI USB 2 0 controller One EHCI controller must always be enabled USB2 0 Pins Routing Route Per Pin Route all Pins to EHCI Route all Pins to xHCI Route USB2 0 pins to E...

Page 92: ...nabled Enable or disable the respective USB3 0 port Legacy USB Support Enabled Disabled Auto Enable USB legacy support Auto option disables legacy support if no USB devices are connected Disable optio...

Page 93: ...to be emulated as hard disk CDROM assumes the CD ROM is formatted as bootable media specified by the El Torito Format Specification 10 4 14 SMART Settings Submenu Feature Options Description SMART Se...

Page 94: ...offering UARTs has been implemented on the carrier board 10 4 16 1 Console Redirection Settings Submenu Feature Options Description Terminal Type VT100 VT100 VT UTF8 ANSI Select terminal type Baudrat...

Page 95: ...led Enabled Enable IPv6 PXE boot support If disabled IPv6 PXE boot option will not be created 10 4 18 Intel R Ethernet Connection I218 LM Submenu Feature Options Description NIC Configuration submenu...

Page 96: ...le PCI Express clock gating for each root port DMI Link ASPM PCH Side Disabled Enabled Active State Power Management ASPM of DMI link PCH side DMI link is the main bus between the Processor and Platfo...

Page 97: ...ower Board Capability SUS_PWR_DN_ACK DeepSx SUS_PWR_DN_ACK Send disabled to PCH DeepSx Show DeepSx policies DeepSx Power Policies Disabled Enabled in S5 Battery Enabled in S4 S5 Battery Enabled in S3...

Page 98: ...link is the main but exclusively internal bus between the Processor and Platform Controller Hub PCH Memory Configuration submenu Memory configuration parameters GT Power Management Control submenu Pro...

Page 99: ...Default 0 The amount of time to wait in nano seconds for switch DDR voltage Max TOLUD Dynamic 1 GB 1 25 GB 1 5 GB 1 75 GB 2 GB 2 25 GB 2 5 GB 2 75 GB 3 GB 3 25 GB Maximum value of TOLUD Dynamic assig...

Page 100: ...t to Slow Exit and PPD when DIMM Exit Mode is set to Fast Exit Memory Remap Enabled Disabled Enable or disable memory remap above 4G GDXC Support Enabled Disabled Enable or disable GDXC support 10 5 2...

Page 101: ...off until the power button is pressed Turn On restores power to the computer Last State restores the previous power state before power loss occurred Note Only works with an ATX type power supply AT Sh...

Page 102: ...NOT be shown during POST For UEFI OS boot the UEFI GOP driver will be installed USB Support Disabled Full Init Partial Init If set to Disabled no USB device will be available before OS boot If set to...

Page 103: ...f UEFI and legacy mass storage device option ROMs Video Option ROM Launch Policy Do Not Launch UEFI ROM Only Legacy ROM Only Legacy ROM First UEFI ROM First Controls the execution of UEFI and legacy v...

Page 104: ...ur for the hard drive to lock using the new password Both user and master password can be set independently however the drive will only lock if a user password is installed 10 7 1 2 Secure Boot Menu S...

Page 105: ...card Changes Discard changes made so far to any of the setup options Stay in setup menu Restore Defaults Restore default values of all the setup options Boot Override List of all boot devices currentl...

Page 106: ...ed feature number and xx is the major and minor revision number The BV87 and BU87 BIOS binary size is 16MB 11 1 Supported Flash Devices The conga TC87 supports the following flash devices Spansion S25...

Page 107: ...password is available if the user can not remember the user password Both passwords can be set independently however the drive will only lock if a user password is installed The max length of the pas...

Page 108: ...Revision 1 0 LPC http developer intel com design chipsets industry lpc htm Universal Serial Bus USB Specification Revision 2 0 http www usb org home PCI Specification Revision 2 3 http www pcisig com...

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