Conexant RC144D, Designer'S Manual

Page: 68 / 88

RC56D, RC336D, and RC144D Modem Device Sets Designer’s Guide
4-10
Conexant
1154
Table 4-3. Programmable Baud Rates
Divisor Latch (Hex)
MS LS Divisor (Decimal) Baud Rate
06 00 1536 75
04 17 1047 110
03 00 768 150
01 80 384 300
00 C0 192 600
00 60 96 1200
00 30 48 2400
00 18 24 4800
00 0C 12 9600
00 06 6 19200
00 04 4 28800
00 03 3 38400
00 02 2 57600
00 01 1 115200
00 00 NA 230400
Note: Values correspond to a UART input frequency of 1.8432 MHz.
4.3 RECEIVER FIFO INTERRUPT OPERATION
4.3.1 Receiver Data Available Interrupt
When the FIFO mode is enabled (FCR0 = 1) and receiver interrupt (RX Data Available) is enabled (IER0 = 1), receiver
interrupt operation is as follows:
1. The Receiver Data Available Flag (LSR0) is set as soon as a received data character is available in the RX FIFO. LSR0
is cleared when the RX FIFO is empty.
2. The Receiver Data Available interrupt code (IIR0-IIR4 = 4h) is set whenever the number of received data bytes in the RX
FIFO reaches the trigger level specified by FCR6-FCR7 bits; it is cleared whenever the number of received data bytes in
the RX FIFO drops below the trigger level specified by FCR6-FCR7 bits.
3. The HINT interrupt is asserted whenever the number of received data bytes in the RX FIFO reaches the trigger level
specified by FCR6-FCR7 bits. HINT interrupt is de-asserted when the number of received data bytes in the RX FIFO
drops below the trigger level specified by FCR6-FCR7 bits.
4.3.2 Receiver Character Timeout Interrupts
When the FIFO mode is enabled (FCR0 = 1) and receiver interrupt (Receiver Data Available) is enabled (IER0 = 1), receiver
character timeout interrupt operation is as follows:
1. A Receiver character timeout interrupt code (IIR0-IIR3 = Ch) is set if at least one received character is in the RX FIFO,
the most recent received serial character was longer than four continuous character times ago (if 2 stop bits are
specified, the second stop bit is included in this time period), and the most recent host read of the RX FIFO was longer
than four continuous character times ago.
4.4 TRANSMITTER FIFO INTERRUPT OPERATION
4.4.1 Transmitter Empty Interrupt
When the FIFO mode is enabled (FCR0 = 1) and transmitter interrupt (TX Buffer Empty) is enabled (IER0 = 1), transmitter
interrupt operation is as follows:
1. The TX Buffer Empty interrupt code (IIR0-IIR3 = 2h) will occur when the TX Buffer is empty; it is cleared when the TX
Buffer is written to (1 to 16 characters) or the IIR is read.
2. The TX Buffer Empty indications will be delayed 1 character time minus the last stop bit time whenever the following
occur: THRE = 1 and there have not been at least two bytes at the same time in the TX FIFO Buffer since the last setting
of THRE was set. The first transmitter interrupt after setting FCR0 will be immediate.