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RC56D, RC336D, and RC144D Modem Device Sets Designer’s Guide

1154

Conexant

4-5

4.2.3 IIR - Interrupt Identifier Register (Addr = 2)

The Interrupt Identifier Register (IIR) identifies the existence and type of up to five prioritized pending interrupts. Four priority
levels are set to assist interrupt processing in the host. The four levels, in order of decreasing priority, are: Highest: Receiver
Line Status, 2: Receiver Data Available or Receiver Character Timeout, 3: TX Buffer Empty, and 4: Modem Status.

When the IIR is accessed, the modem freezes all interrupts and indicates the highest priority interrupt pending to the host.
Any change occurring in interrupt conditions are not indicated until this access is complete.

Bits 7-6

FIFO Mode.

These two bits copy FCR0.

Bits 5-4

Not Used.

Always 0.

Bits 3-1

Highest Priority Pending Interrupt.

These three bits identify the highest priority pending interrupt (Table 4-2). Bit 3 is applicable only when FIFO
mode is selected, otherwise bit 3 is a 0.

Bit 0

Interrupt Pending.

When this bit is a 0, an interrupt is pending; IIR bits 1-3 can be used to determine the source of the interrupt.
When this bit is a1, an interrupt is not pending.

Table 4-2. Interrupt Sources and Reset Control

Interrupt Identification Register

Interrupt Set and Reset Functions

Bit 3

(Note 1)

Bit 2

Bit 1

Bit 0

Priority

Level

Interrupt Type

Interrupt Source

Interrupt Reset Control

0

0

0

1

—

None

None

—

0

1

1

0

Highest

Receiver Line
Status

Overrun Error OE (LSR1),
Parity Error (PE) (LSR2),
Framing Error (FE) (LSR3),
or Break Interrupt (BI) (LSR4)

Reading the LSR

0

1

0

0

2

Received Data
Available

Received Data Available (LSR0) or RX
FIFO Trigger Level (FCR6-FCR7)

Reached

1

Reading the RX Buffer or the
RX FIFO drops below the
Trigger Level

1

1

0

0

2

Character
Time-out

Indication

1

The RX FIFO contains at least 1
character and no characters have been
removed from or input to the RX FIFO
during the last 4 character times.

Reading the RX Buffer

0

0

1

0

3

TX Buffer
Empty

TX Buffer Empty

Reading the IIR or writing to
the TX Buffer

0

0

0

0

4

Modem Status

Delta CTS (DCTS) (MSR0),
Delta DSR (DDSR) (MSR1),
Trailing Edge Ring Indicator (TERI)
(MSR3), or Delta DCD (DCD) (MSR4)

Reading the MSR

Notes:
1. FIFO Mode only.

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Summary of Contents for RC144D

Page 1: ...Doc No 1154 Rev 3 January 22 1999 5 5 DQG 5 0RGHP HYLFH 6HWV IRU HVNWRS SSOLFDWLRQV HVLJQHU V XLGH ...

Page 2: ...in Conexant products Conexant reserves the right to change circuitry at any time without notice This document is subject to change without notice K56flex is a trademark of Conexant Systems Inc and Lucent Technologies Conexant What s Next in Communications Technologies MNP 10EC and ConfigurACE are trademarks of Conexant Systems Inc Product names or services listed in this publication are for identi...

Page 3: ...tputs 1 8 Parallel Host Bus Interface 1 8 NVRAM Serial EEPROM Interface 1 8 External Bus Interface 1 9 Telephone Line Telephone Interface 1 9 Speakerphone Interface SP and SVD Models 1 9 RCDSVD SCP Interface SVD Models 1 9 1 3 5 Commands 1 13 1 3 6 ConfigurACE II for Windows Utility Program 1 13 2 TECHNICAL SPECIFICATIONS 2 1 2 1 SERIAL DTE INTERFACE OPERATION 2 1 2 1 1 Automatic Speed Format Sens...

Page 4: ... Duplex Speakerphone HDSP Mode 2 6 2 12 HOST BASED DSVD MODE 2 7 2 13 FULL DUPLEX SPEAKERPHONE FDSP MODE 2 7 2 14 CALLER ID 2 7 2 15 WORLD CLASS COUNTRY SUPPORT 2 7 2 15 1 Dialing 2 7 2 15 2 Carrier Transmit Level 2 7 2 15 3 Calling Tone 2 7 2 15 4 Call Progress Tone Detection 2 7 2 15 5 Answer Tone Detection 2 8 2 15 6 Blacklist Parameters 2 8 2 15 7 Relay Control 2 8 2 16 DIAGNOSTICS 2 8 2 16 1 ...

Page 5: ...tter Empty Interrupt 4 10 5 DESIGN CONSIDERATIONS 5 1 5 1 PC BOARD LAYOUT GUIDELINES 5 1 5 1 1 General Principles 5 1 5 1 2 Component Placement 5 1 5 1 3 Signal Routing 5 2 5 1 4 Board Power Traces 5 3 5 1 5 MCU Power 5 3 5 1 6 MDP Power and Ground 5 3 5 1 7 Ground Planes 5 3 5 1 8 Crystal Circuit 5 4 5 1 9 Standalone Modem Design with EIA TIA 232 Interface 5 4 5 1 10 VC and VREF Circuit 5 4 5 1 1...

Page 6: ... Interface 80 Pin PQFP 3 4 Figure 3 4 MCU Pin Signals Parallel Host Interface 80 Pin PQFP 3 4 Figure 3 5 MDP Pin Signals 100 Pin PQFP 3 7 Figure 3 6 RCDSVD SCP Pin Signals 100 Pin PQFP 3 9 Figure 3 7 Waveforms External Memory Bus 3 24 Figure 3 8 Waveforms Parallel Host Bus 3 26 Figure 3 9 Waveforms Serial DTE Interface 3 27 Figure 5 1 Interface Schematic MCU with Serial DTE Interface 80 Pin PQFP 5...

Page 7: ...VD SCP Pin Signal Definitions 3 17 Table 3 8 MCU Digital Electrical Characteristics 3 19 Table 3 9 MDP Digital Electrical Characteristics 3 20 Table 3 10 Analog Electrical Characteristics 3 21 Table 3 11 Current and Power Requirements 3 22 Table 3 12 Absolute Maximum Ratings 3 22 Table 3 13 Timing External Memory Bus 3 23 Table 3 14 Timing Parallel Host Bus 3 25 Table 4 1 Parallel Interface Regist...

Page 8: ...RC56D RC336D and RC144D Modem Device Sets Designer s Guide viii Conexant 1154 This page is intentionally blank ...

Page 9: ...s Error correction V 42 MNP 2 4 and data compression V 42 bis MNP 5 maximize data transfer integrity and boost average data throughput up to 230 4 kbps Non error correcting mode is also supported In V 32 bis mode the modem operates at line speeds up to 14 4 kbps The modem supports fax Group 3 send and receive rates up to 33 6 kbps and T 30 protocol In voice TAM mode enhanced 2 bit or 4 bit per sam...

Page 10: ...EHU 0 8 34 3 3DUW 1R 0 3 34 3 3DUW 1R 8 8 3 3DUW 1R 5 69 34 3 3DUW 1R 9 DQG IOH DWD 9 DWD 9 D D O DQG 9RLFH 7 0 RVW 69 ODVV 9 63 XGLR6SDQ 2Q ERDUG 69 5 63 86 6 5 5 5 86 6 5 5 1RWHV 0RGHO RSWLRQV RZQORDGDEOH 63 6SHDNHUSKRQH 313 QFOXGHV 3Q3 QWHUIDFH HYLFH SLQ 34 3 69 2Q ERDUG 69 ZLWK 5 69 6 3 DQG 6SHDNHUSKRQH 86 8QLYHUVDO 6HULDO XV LQWHUIDFH ZLWK 8 8 GHYLFH 6XSSRUWHG IXQFWLRQV 6XSSRUWHG 1RW VXSSRUWH...

Page 11: ...pan simultaneous audio voice and data SP and SVD models ITU T V 61 modulation 4 8 kbps data with audio Handset headset or microphone speaker ITU T V 70 DSVD using the RCDSVD SCP SVD models ITU T interoperable G 729 and G 729 Annex A with interoperable G 729 Annex B Voice silence detection and handset echo cancellation Robust DSVD timing recovery Handset headset or half duplex speakerphone Host bas...

Page 12: ... connect at the highest data rate that the channel can support from 33 6 kbps to 300 bps with automatic fallback Automode operation in V 34 is provided in accordance with PN3320 and in V 32 bis in accordance with PN2330 All tone and pattern detection functions required by the applicable ITU or Bell standard are supported In fax modem mode the modem can operate in 2 wire half duplex synchronous mod...

Page 13: ...RC336 RC144 RAM 1M 128K x 8 RC56 RC336 RC144 or 32K x 8 RC336 RC144 Figure 1 1 Block Diagram Serial DTE Interface 1154F1 2 BD Par TELEPHONE LINE TELEPHONE HANDSET TELEPHONE EXTENSIONS AUDIO INTERFACE CIRCUIT TELEPHONE LINE TEL HANDSET MICROPHONE HEADPHONE SPEAKER MODEM DEVICE SET MICRO CONTROLLER UNIT MCU 80 PIN PQFP MODEM DATA PUMP MDP 100 PIN PQFP PARALLEL HOST BUS INTERFACE RCDSVD SPEECH CODEC ...

Page 14: ...ous audio voice and data over a telephone line at a data rate of 4800 bps with audio using V 61 modulation AudioSpan can send any type of audio waveform including music Data can be sent with or without error correction The audio voice interface can be in the form of a headset handset or a microphone and speaker Handset echo cancellation is provided DSVD Mode using RCDSVD SCP Device SVD Models On b...

Page 15: ...ission supports sending data at speeds up to V 34 rates In V 34 data modem mode the MDP can operate in 2 wire full duplex synchronous asynchronous modes at line rates up to 33 6 kbps Using V 34 modulation to optimize modem configuration for line conditions the MDP can connect at the highest data rate that the channel can support from 33 6 kbps to 300 bps with automatic fallback Automode operation ...

Page 16: ... modem firmware may also be provided in source code form under a source code addendum license agreement 1 3 4 Supported Interfaces The major hardware signal interfaces of the modem device set are identified in Figure 1 1 serial DTE interface and Figure 1 2 parallel host bus interface Serial DTE Interface and Indicator Outputs A V 24 EIA TIA 232 E logic compatible serial DTE interface is selected b...

Page 17: ...nction can be enabled by ConfigurACE II RLY3 Mute MUTE if needed can be enabled by ConfigurACE II RLY4 Caller ID CALLID if needed The DAAs shown in Figure 1 3 and Figure 1 4 support the Caller ID function without use of a separate relay Ring signal RINGD and loop current sense LCS inputs are supported MDP A single ended receive analog input RIN and a differential transmit analog output TXA1 TXA2 a...

Page 18: ...PHONY EXTENSIONS INTERFACE CIRCUIT HEADPHONE MICROPHONE RINGD OH VC BIAS AMP SOUNDUCER OPTIONAL AUDIO HEADPHONE INTERFACE CIRCUIT SSI BRDGE OH RELAY HYBRD XFRMR TEL LINE TEL HANDSET SURG PROT MICV SPK TXA1 RIN TXA2 RNG DET SP OR SVD MODELS NON SP OR SVD MODELS EXTENSION PICKUP REMOTE HANG UP EXTOH MICM Figure 1 3 1 Relay Data Fax TAM DAA Interface U S ...

Page 19: ...IONS INTERFACE CIRCUIT HEADPHONE MICROPHONE LCS RINGD VOICE OH VC BIAS AMP SOUNDUCER OPTIONAL AUDIO HEADPHONE INTERFACE CIRCUIT SSI BRDGE OH RELAY HYBRD XFRMR TEL LINE TEL HANDSET VOICE RELAY LCS CUR SRC RNG DET SURG PROT MICV SPK HANDSET HYBRID TELOUT TELIN TXA1 RIN TXA2 EXTENSION PICKUP REMOTE HANG UP EXTOH Figure 1 4 2 Relay Data Fax TAM V 61 Speakerphone DAA Interface U S ...

Page 20: ...tion X 11 M1 External Microphone connected to the DCE DCE on hook Local phone connected to the line X 12 M1ST External Microphone and Internal Speaker connected to the line DCE off hook DCE connected to the line Local phone provided with power to detect hook condition X 13 M1S1T External Microphone and External Speaker connected to the line DCE off hook DCE connected to the line Local phone provid...

Page 21: ...DSP functions operate in response to speakerphone commands when FCLASS 8 and VSP 1 is selected World Class W Class Operation All models operate in response to W class AT commands 1 3 6 ConfigurACE II for Windows Utility Program The PC based ConfigurACE II for Windows utility program allows the OEM to customize the modem firmware to suit specific application and country requirements ConfigurACE II ...

Page 22: ...RC56D RC336D and RC144D Modem Device Sets Designer s Guide 1 14 Conexant 1154 This page is intentionally blank ...

Page 23: ...rate at rates up to 230400 bps by programming the Divisor Latch in the parallel interface registers if supported by communications software and or driver a Windows 95 driver is available from Conexant Fax Modem Mode In V 17 and V 34 fax modes the modem can operate at rates up to 230 4 kbps by programming the Divisor Latch in the parallel interface registers if supported by communications software ...

Page 24: ... Automode detection can be enabled by the MS command to allow the modem to connect to a remote modem in accordance with draft PN 3320 for V 34 Table 2 1 Table 2 1 MS Command Automode Connectivity mod Modulation Possible Rates bps 1 Notes V21 V 21 300 V22 V 22 1200 V22B V 22 bis 2400 or 1200 V23 V 23 1200 See Note 2 V32 V 32 9600 or 4800 V32B V 32 bis 14400 12000 9600 7200 or 4800 V34 V 34 33600 31...

Page 25: ...or correction mode the modem disconnects after receiving 1 6 10 seconds of continuous SPACE Send SPACE on Disconnect V 22 bis and Below If selected by the Y1 command in non error correction mode the modem sends 4 10 seconds of continuous SPACE when a locally commanded hang up is issued by the Dn or H command Fall Forward Fallback V 34 V 32 bis V 32 During initial handshake the modem will fallback ...

Page 26: ...re transmitting it to the remote modem and by decompressing encoded received data before sending it to the DTE 2 6 MNP 10 DATA THROUGHPUT ENHANCEMENT MNP 10 protocol and MNP Extended Services enhance performance under adverse channel conditions such as those found in rural long distance or cellular environments An MNP 10 connection is established when an MNP 2 4 connection is negotiated with a rem...

Page 27: ...n is available at the 7200 Hz sample rate 2 9 3 Voice Transmit Mode This mode is entered when the VTX command is active in order to playback voice or audio data to the TXA output typically to a speaker handset or to the telephone line Digitized voice data is decompressed and converted to analog form at the original compression quantization sample per bits rate then output to the TXA output Digitiz...

Page 28: ...ality Considerations AudioSpan audio quality is dependent upon telephone line quality Higher quality telephone lines provide better audio quality than impaired telephone lines 2 11 ON BOARD DSVD MODE On Board DSVD operation is enabled by the SMS 1 and the FCLASS 0 commands In On Board DSVD Mode the RCDSVD SCP is connected to a MCU and to a handset or to a microphone speaker arrangement e g in a sp...

Page 29: ...aller ID can be enabled disabled using the CID command When enabled caller ID information date time caller code and name can be passed to the DTE in formatted or unformatted form Inquiry support allows the current caller ID mode and mode capabilities of the modem to be retrieved from the modem 2 15 WORLD CLASS COUNTRY SUPPORT W class functions support modem operation in a multiple countries The fo...

Page 30: ...loops the data back to the local DTE 2 16 2 Power On Reset Tests Upon power on the modem performs tests of the modem internal and external RAM and NVRAM If the modem internal RAM or external RAM test fails the TMIND output is pulsed serial interface version or the DCD bit in the parallel interface register is pulsed parallel interface version as follows Internal or external RAM test fails One puls...

Page 31: ...ments for the 100 pin PQFP are shown in Figure 3 5 and are listed in Table 3 3 The RCDSVD SCP pin assignments for the 100 pin PQFP are shown in Figure 3 6 and are listed in Table 3 4 The MCU hardware interface signals are defined in Table 3 5 The MDP hardware interface signals are defined in Table 3 6 The RCDSVD SCP hardware interface signals are defined in Table 3 7 The MCU digital electrical cha...

Page 32: ...CLKIN VDD CLKOUT VD3 3 RCDSVD SCP R6715 RESET CS IRQ1 A0 A4 D0 D7 READ WRITE MICIN SPKP LINEIN LINEOUT WKRESOUT SCPSEL SCPIRQ DGND AGND VDD AVDD VAA VCC 5V VCC 5V VCC 5V VDD VCC 5V DGND NVMDATA NVMCLK NVRAM OPTIONAL MODEM CRYSTAL CIRCUIT XTLI XTLO EXTOH RLY1 OH RLY2 VOICE RLY3 MUTE RLY4 CALLID LCS RINGD DTE SERIAL INDICATOR INTERFACE XTCLK TXCLK RXCLK TXD RXD CTS DSR RLSD TM RI DRSOUT DTR RTS RDL ...

Page 33: ...PARALLEL HOST BUS INTERFACE HD0 HD7 HA0 HA2 HCS HWT HRD HINT RES A0 A16 D0 D7 READ WRITE RAMSEL A0 A17 D0 D7 READ WRITE ROMSEL VGG AVDD VAA DGND AGND VCC 5V VCC 5V VCC 5V CLKIN VDD CLKOUT VD3 3 RCDSVD SCP R6715 RESET CS IRQ1 A0 A4 D0 D7 READ WRITE MICIN SPKP LINEIN LINEOUT WKRESOUT SCPSEL SCPIRQ DGND AGND VDD AVDD VAA VCC 5V VCC 5V VCC 5V VDD VCC 5V DGND NVMDATA NVMCLK NVRAM OPTIONAL MODEM CRYSTAL...

Page 34: ...7 RAMSEL ROMSEL DPSEL A16 GND RLY2 VOICE RLY1 OH A15 A14 A13 A12 A11 A10 A9 A8 A7 Figure 3 3 MCU Pin Signals Serial DTE Interface 80 Pin PQFP 1154F3 4 PO MCU80F Par 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RES ...

Page 35: ... EB A7 22 PD1 It Ot1 6 NC 62 A8 Ot1 6 EB A8 23 PD2 It Ot1 6 NC 63 A9 Ot1 6 EB A9 24 PD3 STPMODE It VCC 64 A10 Ot1 6 EB A10 25 PD4 DTR It DTE IF DTR 65 A11 Ot1 6 EB A11 26 PD5 AL It DTE IF AL 66 A12 Ot1 6 EB A12 27 PD6 RTS It DTE IF RTS 67 A13 Ot1 6 EB A13 28 PD7 DPIRQ It MDP IRQ 68 A14 Ot1 6 EB A14 29 GND GND GND 69 A15 Ot1 6 EB A15 30 PE4 LCS It DAA LCS 70 PE0 RLY1 Ot6 DAA OH 31 CLKOUT Ot1 6 MDP ...

Page 36: ...A6 Ot1 6 EB A6 21 PD0 HA0 It HB HA0 61 A7 Ot1 6 EB A7 22 PD1 HA1 It HB HA1 62 A8 Ot1 6 EB A8 23 PD2 HA2 It HB HA2 63 A9 Ot1 6 EB A9 24 PD3 STPMODE It VCC 64 A10 Ot1 6 EB A10 25 PD4 HCS It HB CS 65 A11 Ot1 6 EB A11 26 PD5 HWT It HB WT thru 180Ω 66 A12 Ot1 6 EB A12 27 PD6 HRD It HB RD thru 180Ω 67 A13 Ot1 6 EB A13 28 PD7 DPIRQ It MDP IRQ 68 A14 Ot1 6 EB A14 29 GND GND GND 69 A15 Ot1 6 EB A15 30 PE4 ...

Page 37: ...D3 D2 D1 D0 NC CLKIN VDD RESERVED RESERVED GP00 GND TXA2 VREF VC MICV NC RIN RES2 MICM SPKMD AGND AVDD MCNTRLSIN MCLKIN MTXSIN MSCLK MRXOUT MSTROBE RLYA AGND GND VSTROBE NC IRQ RINGD RI RESERVED XCLK YCLK RESERVED RESERVED RESERVED VGG RESERVED SLEEPO VDD RXD RESERVED GND XTCLK VDD SR1IO RESERVED SR2IO SA2CLK RESERVED RESERVED IASLEEP VCNTRLSIN NC VCLKIN NC VTXSIN NC VSCLK NC VRXOUT NC RESERVED RS...

Page 38: ... AGND GND AGND 75 YCLK OA NC 26 TELIN NC I DA L A IF 76 XCLK OA NC 27 TELOUT NC O DD L A IF 77 RESERVED NC 28 AVAA PWR 5VA 78 RI OA NC 29 SPK O DF L A IF 79 RINGD IA MCU VD3 3 30 TXA1 O DD L A IF 80 IRQ IA MCU DPIRQ 31 TXA2 O DD L A IF 81 GND GND DGND 32 VREF REF VC through capacitors 82 GP00 DI MDP RDCLK 8 33 VC REF DAA through FB GND through capacitors and FB 83 RESERVED NC 34 MICV NC I DA L A I...

Page 39: ...VSS NC GPO4 GPO5 GPO6 GPO7 NC NC VDD NC NC NC NC READ CS NC RS4 RS3 RS2 RS1 RS0 VDD D7 D6 D5 D4 D3 D2 D1 D0 WRITE ADVSS NC NC VC VREF VSS NC RBIAS MICIN AVSS LINEIN AVDD NC NC ADVSS NC LINEOUT SPKN SPKP NC FSYNC ICLK NC NC REFCNTL NC NC VSS IARESET MCLK ADVDD SIN SOUT CTRLSIN IACLK 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82...

Page 40: ...it 24 MICIN I DA L A IF MICV 74 XTLO O Crystal Clock Circuit 25 AVSS GND AGND 75 NC NC 26 LINEIN I DA L A IF TELIN 76 NC NC 27 AVDD PWR VCC through filter 77 VDD PWR VCC 28 NC NC 78 NC NC 29 NC NC 79 SR3IN DI SCP SOUT 48 30 ADVSS GND GND 80 VSS GND DGND 31 NC NC 81 VSS GND DGND 32 LINEOUT O DD L A IF TELOUT 82 NC NC 33 SPKN O DF NC 83 NC NC 34 SPKP O DF L A IF SPK 84 NC NC 35 NC NC 85 NC NC 36 FSY...

Page 41: ...P Connect to MDP VDD NMI Is2pu Non Maskable Interrupt Not used Connect to VCC TST Is2pu Test Mode Factory test only Leave open STPMODE PD3 It Stop Mode Not used Connect to VCC DPIRQ PD7 It MDP Interrupt Request Connect to the MDP IRQ output PARIF PE6 Itpu Parallel Serial Interface MCU PARIF input high or open selects parallel host interface PARIF low selects serial DTE interface MCUP Not used leav...

Page 42: ...andset or an extension phone PARALLEL HOST INTERFACE PARALLEL HOST INTERFACE CONFIGURATION The parallel interface emulates a 16550A UART compatible interface HA0 HA2 PD0 PD2 It Host Bus Address Lines 0 2 During a host read or write operation with HCS low HA0 HA2 select an internal MCU 16550A compatible register HD0 HD7 PC0 PC7 It Ot6 Host Bus Data Lines 0 7 HD0 HD7 are comprised of eight three sta...

Page 43: ...T142 The TM output indicates the modem is in test mode low or in any other mode high RI PC5 Ot6 Ring Indicator EIA CE ITU T CT125 RI output ON low indicates the presence of an ON segment of a ring signal on the telephone line DRSOUT PC3 Ot6 Data Signaling Rate Indicator DRSOUT is ON low when the modem desires or is engaged in the high speed 4800 bps or higher mode DRSOUT is OFF high otherwise DTR ...

Page 44: ...lock Divided by 2 Output clock at one half the external crystal frequency which runs during MDP Normal Mode and is turned off during Sleep Mode Leave open PLLVDD PLL PLLVDD Connection Connect to 3 3V VDD through 10 Ω and to DGND through 10 µF PLLGND PLL PLLGND Connection Connect to DGND MCU INTERFACE CLKIN I Clock In Connect to the MCU CLKOUT pin WKRES IA Wake up Reset WKRES is connected internall...

Page 45: ...cross the relay coil An external transistor can be used to drive heavier loads e g electro mechanical relays RLYA is controlled by host setting resetting of the RA bit MICM I DA Modem Microphone Input MICM is a single ended microphone input The input impedance is 70k Ω NOTE If not used do not tie directly to ground this input has a bias voltage of 2 5V VAA 5V MICV NC I DA Voice Microphone Input MI...

Page 46: ...RLSIN DI MDP SR1IO VSCLK NC DI MDP SR2CLK VCNTRLSIN NC DI MDP SR2IO MRXOUT DI MDP SR4IN VTXSIN NC DI MDP SR3OUT VRXOUT NC DI MDP SR3IN MTXSIN DI MDP SR4OUT SR2IO DI MDP VCNTRLSIN SR4IN DI MDP MRXOUT SR2CLK DI MDP VSCLK SA2CLK DI MDP VSTROBE SR3OUT DI MDP VTXSIN IA2CLK I O Connect to 3 3V RESERVED Reserved Function May be connected to internal circuit Leave open Notes 1 I O types IA IC Digital inpu...

Page 47: ...nd MODEM INTERFACE D0 D7 IA OB Data Lines Connect to the modem external bus D0 D7 lines respectively RS0 RS4 IA Register Select Lines Connect to the modem external bus A0 A4 lines respectively CS IA Chip Select Connect to the modem SVDCS line READ IA Read Enable Connect to the modem external bus READ line WRITE IA Write Enable Connect to the modem external bus WRITE line IRQ IA Interrupt Request C...

Page 48: ... DI Connect to SCP SR3IN SR4OUT DI Connect to SCP SIN SIN DI Connect to SCP SR4OUT IACLK DI Connect to SCP MCLK MCLK DI Connect to SCP IACLK IA1CLK DI Connect to SCP ICLK ICLK DI Connect to SCP IA1CLK SA1CLK DI Connect to SCP FSYNC FSYNC DI Connect to SCP SA1CLK SPKN O DF Leave open NC REFCNTL REF Connect to GND Notes 1 I O types DI Device interconnect IA IC ID Digital input see Table 3 9 OA OB Di...

Page 49: ... compatible Note 3 Output High Voltage VOH 2 4 V ILOAD 100 µA Output Low Voltage VOL 0 4 V ILOAD 1 6 mA 3 State Output High Z Current IOZ 10 µA VIN 0 V to VCC Ot6 Output TTL compatible PC0 PC7 PE0 PE7 Note 3 Output High Voltage VOH 2 4 V ILOAD 6 mA Output Low Voltage VOL 0 4 V ILOAD 6 mA 3 State Output High Z Current IOZ 10 µA VIN 0 V to VCC Ot Output CMOS PA3 PA4 Note 3 Output High Voltage VOH 2 ...

Page 50: ...h Voltage VIH Vdc Type IA 2 0 VCC Input High Current IIH 40 µA Input Low Voltage VIL 0 3 0 8 VDC Input Low Current IIL 40 µA Input Leakage Current IIN 100 µADC VIN 0 to 3 3V VCC 3 6V Output High Voltage VOH VDC Type OA 2 4 VCC ILOAD 100 µA Type OD ILOAD 0 mA Output Low Voltage VOL VDC Type OA 0 4 ILOAD 1 6 mA Type OD 0 75 ILOAD 15 mA Three State Off Current ITSI 10 µADC VIN 0 4 to VCC 1 ...

Page 51: ...nge 1 1 VP P Reference Voltage 2 5 VDC DC Offset Voltage 20 mV RCDSVD SCP LINEIN I DA Input Impedance 38K Ω AC Input Voltage Range 2 0 VP P Single ended Reference Voltage 2 5 VDC LINEOUT O DD Minimum Load 350 Ω Maximum Capacitive Load 0 12 µF Output Impedance 10 Ω AC Output Voltage Range 2 2 VP P Single ended Reference Voltage 2 5 VDC DC Offset Voltage 200 mV SPKP and SPKN O DF Minimum Load 300 Ω ...

Page 52: ... 630 Sleep 10 50 Notes 1 Test conditions MCU PnP and SCP VDD 5 0 VDC for typical values VCC 5 25 VDC for maximum values MDP VDD 3 3 VDC for typical values VCC 3 6 VDC for maximum values 2 Normal operating voltage MCU PnP and SCP VDD 5 0 V 5 MDP VDD 3 3 0 3 V Table 3 12 Absolute Maximum Ratings Parameter Symbol Limits Units Supply Voltage VDD MCU 0 5 to 6 0 MDP 0 5 to 4 6 V Input Voltage VIN 0 5 to...

Page 53: ...s tRDH READ High to Read Data Hold 0 ns Write tAS WRITE High to Address Valid 11 2 12 5 ns tES WRITE High to ES Valid 12 2 13 5 ns tWW WRITE to WRITE Pulse Width 17 72 124 01 ns tWTD WRITE Low to Write Data Valid 7 1 8 0 ns tWTH WRITE High to Write Data Hold 5 0 ns Notes 1 ES RAMSEL or ROMSEL 2 Read pulse width and write pulse width RAM tRW tWW 0 5 tCYC 17 72 for Non Extended Cycle Timing ROM tRW ...

Page 54: ...ng Read Timing t CYC t AS RDH C2 A0 A16 t RW t t RDS READ D0 D7 ES t ES C2 Internal Phase 2 clock ES RAMSEL ROMSEL or SVDCS 1105F3 8 EB WF t CYC t AS t WW t t WTH WTD ES t C2 A0 A16 WRITE D0 D7 ES C2 Internal Phase 2 clock ES RAMSEL ROMSEL or SVDCS Figure 3 7 Waveforms External Memory Bus ...

Page 55: ...d 10 ns tWT HWT Strobe Width 50 ns tDS Write Data Setup see Note 4 35 ns tDWH Write Data Hold see Note 5 5 ns Notes 1 When the host executes consecutive Rx FIFO reads a minimum delay of 2 times the internal CPU clock cycle plus 15 ns 85 86 ns at 28 224 MHz is required from the falling edge of HRD to the falling edge of the next Host Rx FIFO HRD clock 2 When the Host executes consecutive Tx FIFO wr...

Page 56: ... Sets Designer s Guide 3 26 Conexant 1154 tAS tAH tCS tCH tRD tDF tDD tDRH HA0 HA2 HCS HRD HWT HD0 HD7 tAS tAH tCS tCH HA0 HA2 tWT tDS tDWH HCS HRD HWT HD0 HD7 1154F3 8 HB WF a Host Read b Host Write Figure 3 8 Waveforms Parallel Host Bus ...

Page 57: ...CLK 9600 BPS TXD 9600 BPS NOTE THIS FIGURE IS VALID FOR SYNCHRONOUS MODE ONLY THERE IS NO RELATIONSHIP BETWEEN NOTE TXD AND TDCLK IN ASYNCHRONOUS MODE RDCLK 4800 BPS RXD 4800 BPS RDCLK 9600 BPS RXD 9600 BPS NOTE THIS FIGURE IS VALID FOR SYNCHRONOUS MODE ONLY THERE IS NO RELATIONSHIP BETWEEN NOTE RXD AND RDCLK IN ASYNCHRONOUS MODE a Transmit b Receive 91354 7 1096F3 13 DTE Ser WF Figure 3 9 Wavefor...

Page 58: ...RC56D RC336D and RC144D Modem Device Sets Designer s Guide 3 28 Conexant 1154 This page is intentionally blank ...

Page 59: ...O Control Register FCR0 1 both FIFOs are operative Furthermore when FIFO mode is selected DMA operation of the FIFO can also be selected FCR3 1 When FIFO mode is not selected operation is restricted to 16450 interface operation The received data is read by the host from the Receiver Buffer RX Buffer The RX Buffer corresponds to the Receiver Buffer Register in a 16550A device In FIFO mode the RX FI...

Page 60: ...Set Break Stick Parity Even Parity Select EPS Parity Enable PEN Number of Stop Bits STB Word Length Select Bit 1 WLS1 Word Length Select Bit 0 WLS0 2 Interrupt Identify Register IIR Read Only FIFOs Enabled FIFOs Enabled 0 0 Pending Interrupt ID Bit 2 Pending Interrupt ID Bit 1 Pending Interrupt ID Bit 0 0 if Interrupt Pending 2 FIFO Control Register FCR Write Only Receiver Trigger MSB Receiver Tri...

Page 61: ...the Delta CTS MSR0 Delta DSR MSR1 Delta TER MSR2 or Delta DCD MSR3 bit in the Modem Status Register MSR is a 1 This bit when a 0 disables assertion of HINT due to setting of any of these four MSR bits Bit 2 Enable Receiver Line Status Interrupt ELSI This bit when a 1 enables assertion of the HINT output whenever the Overrun Error LSR1 Parity Error LSR2 Framing Error LSR3 or Break Interrupt LSR4 re...

Page 62: ...racter timeout IIR0 IIR3 Ch has occurred RXRDY will go inactive when there are no more characters in the RX FIFO TXRDY will be asserted when there are one or more empty unfilled locations in the TX FIFO TXRDY will go inactive when the TX FIFO is completely full Non DMA operation in FIFO mode RXRDY will be asserted when there are one or more characters in the RX FIFO RXRDY will go inactive when the...

Page 63: ...rrupt Pending When this bit is a 0 an interrupt is pending IIR bits 1 3 can be used to determine the source of the interrupt When this bit is a1 an interrupt is not pending Table 4 2 Interrupt Sources and Reset Control Interrupt Identification Register Interrupt Set and Reset Functions Bit 3 Note 1 Bit 2 Bit 1 Bit 0 Priority Level Interrupt Type Interrupt Source Interrupt Reset Control 0 0 0 1 Non...

Page 64: ...R3 and LCR4 bits Bit 4 Even Parity Select EPS When parity is enabled LCR3 1 and stick parity is not selected LCR5 0 the number of 1s transmitted or checked by the receiver in the data word bits and parity bit is either even LCR4 1 or odd LCR4 0 Bit 3 Enable Parity PEN When bit 3 is a 1 a parity bit is generated in the serial out transmit data stream and checked in the serial in receive data stream...

Page 65: ...S MCR1 Out1 MCR2 and Out2 MCR3 modem control register bits are internally connected to the DSR MSR5 CTS MSR4 RI MSR6 and DCD MSR7 modem status register bits respectively Bit 3 Output 2 When this bit is a 1 HINT is enabled When this bit is a 0 HINT is in the high impedance state Bit 2 Output 1 This bit is used in local loopback see MCR4 Bit 1 Request to Send RTS This bit controls the Request to Sen...

Page 66: ...logic 0 for longer than two full word lengths plus 3 bits The BI bit is reset when the host reads the LSR Bit 3 Framing Error FE This bit indicates that the received character did not have a valid stop bit The FE bit is set to a 1 whenever the stop bit following the last data bit or parity bit is detected as a logic o space The FE bit is reset to a 0 when the host reads the LSR In the FIFO mode th...

Page 67: ...tect DDCD This bit is set to a 1 when the DCD bit changes state since the MSR was last read by the host Bit 2 Trailing Edge of Ring Indicator TERI This bit is set to a 1 when the RI bit changes from a 1 to a 0 state since the MSR was last read by the host Bit 1 Delta Data Set Ready DDSR This bit is set to a 1 when the DSR bit has changed since the MSR was last read by the host Bit 0 Delta Clear to...

Page 68: ...bits HINT interrupt is de asserted when the number of received data bytes in the RX FIFO drops below the trigger level specified by FCR6 FCR7 bits 4 3 2 Receiver Character Timeout Interrupts When the FIFO mode is enabled FCR0 1 and receiver interrupt Receiver Data Available is enabled IER0 1 receiver character timeout interrupt operation is as follows 1 A Receiver character timeout interrupt code ...

Page 69: ...er engineering practices are beyond the scope of this designer s guide The designer should consult noise suppression techniques described in technical publications and journals electronics and electrical engineering text books and component supplier application notes Seminars addressing noise suppression techniques are often offered by technical and professional associations as well as component s...

Page 70: ...th b Place 0 1 µF decoupling bypass capacitors close to the pins usually power and ground of the IC they are decoupling Make the smallest loop area possible between the capacitor and power ground pins to reduce EMI c For parallel host bus models place host bus interface components close to the edge connector in accordance with the applicable bus interface standard e g use a 2 5 in maximum trace le...

Page 71: ... parallel with a ceramic 0 1 µF capacitor between 5V power and ground at one or more points in the digital section Place one set nearest to where power enters the PCB edge connector or power connector and place another set at the furthest distance from where power enters the PCB These capacitors help to supply current surge demands by the digital circuits and prevent those surges from generating n...

Page 72: ... and as direct i e not going through vias as possible 5 1 8 Crystal Circuit 1 Keep all traces and component leads connected to crystal input and output pins i e XTLI and XTLO short in order to reduce induced noise levels and minimize any stray capacitance that could affect the crystal oscillator Keep the XTLO trace extremely short with no bends greater than 45 degrees and containing no vias since ...

Page 73: ...margin 2 Various grounding areas connected by tie points these tie points can be short jumper wires solder bridges between close traces etc 3 EIA TIA 232 cable ground wire or cable shielding connected on the board or floated 4 Develop two designs in parallel one based on a 2 layer board and the other based on a 4 layer board During the evaluation phase better performance of one design over another...

Page 74: ...rface 5 6 30 32 49 50 70 71 Host Bus Interface 13 23 25 27 79 80 No Connection NC 7 31 34 38 77 MDP VDD AVDD AVAA VGG PLLVDD 28 40 63 71 85 98 100 Pin PQFP GND DGND AGND PLLGND 16 25 39 48 49 65 81 99 100 Crystal Clock 75 76 86 87 Control 9 17 36 56 69 Line Interface 47 26 27 30 35 37 79 Speaker Interface 29 38 Serial LED Interface 8 12 13 64 82 11 67 68 78 Host Interface 2 7 88 97 80 MDP Intercon...

Page 75: ... and 19 5 pF Frequency Stability vs Temperature 35 ppm 0 C to 70 C vs Aging 15 ppm 4 years Oscillation Mode Fundamental Calibration Mode Parallel resonant Load Capacitance CL 18 pF nom Shunt Capacitance CO 7 pF max Series Resistance R1 60 Ω max 20 nW drive level Drive Level 100µW correlation 300µW max Operating Temperature 0 C to 70 C Storage Temperature 40 C to 85 C Mechanical Dimensions L x W x ...

Page 76: ...m Shunt Capacitance CO 7 pF max Series Resistance R1 35 Ω max 20 nW drive level Drive Level 100µW correlation 500µW max Operating Temperature 0 C to 70 C Storage Temperature 40 C to 85 C Mechanical Dimensions L x W x H 11 05 x 4 65 x 13 46 mm max Mounting Through Hole Holder Type HC 49 U Suggested Suppliers KDS America ILSI America Vectron Technologies Inc Notes 1 Characteristics 25 C unless other...

Page 77: ... Supply Voltage 5 0V 10 Supply Current 3 45 mA max Storage Temperature 55 C to 125 C Mechanical Dimensions L x W x H 7 64 x 5 23 x 1 95 mm max Mounting SMT Package Ceramic Leadless Chip Carrier Suggested Suppliers KDS America ILSI America Vectron Technologies Inc Notes 1 Inclusive of calibration tolerance 25 C over the operating temperature range and aging 2 Transition times are measured between 1...

Page 78: ...ive Output High Z 4 0 V min 0 8 V max Supply Voltage 5 0 V 10 Supply Current 3 25 mA max Storage Temperature 55 C to 125 C Mechanical Dimensions L x W x H 13 2 x 13 2 x 5 0 mm max Mounting Through Hole Package Half Size 8 Pin DIP Notes 1 Inclusive of calibration tolerance 25 C over the operating temperature range and aging 2 Transition times are measured between 10 and 90 of Supply Voltage 3 Curre...

Page 79: ...ckaged in an 80 pin PQFP with parallel host interface is shown in Figure 5 2 A typical interface schematic for the MDP packaged in a 100 pin PQFP is shown in Figure 5 3 A typical interface schematic for the SCP packaged in a 100 pin PQFP is shown in Figure 5 4 Consult AccelerATor Kits or reference designs for full schematics of typical applications A complete schematic for a parallel host applicat...

Page 80: ...AM CIRCUIT 10K VCC 1154F5 1 SC MC80FP TELEPHONE LINE INTERFACE XTLI XTLO PARIF STPMODE GND GND GND GND GND VDD VDD NMI TST PSC 9 10 49 24 72 53 52 29 12 8 51 2 40 7 0 1 NC ROM RAM MDP MDP SCP SCP MDP MDP MDP SCP MDP VCC 10K 100 33 pF 33 pF NC 28 224 MHz NC NC 35 36 34 38 13 14 15 16 18 19 20 25 26 27 21 17 80 TXCLK RXCLK SCPIRQ TXD RXD DSR CTS RLSD DRSOUT RI TM RDL DTR AL RTS DTRIND AAIND TMIND DT...

Page 81: ...5 37 38 70 71 5 6 30 32 50 RESERVED RESERVED RESERVED RESERVED RLY1 RLY2 RLY3 RLY4 LCS RINGD EXTOH VCC 10K 33 39 NVRAM CIRCUIT 10K VCC 1154F5 2 SC MC80FP TELEPHONE LINE INTERFACE HOST PARALLEL BUS INTERFACE XTLI XTLO PARIF HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HA0 HA1 HA2 HCS HWT HRD HINT RES STPMODE GND GND GND GND GND VDD VDD NMI TST PSC 9 10 49 13 14 15 16 17 18 19 20 21 22 23 25 26 27 80 1 24 72 53 ...

Page 82: ... 62 24 23 20 18 22 19 21 59 10 60 55 52 50 51 53 54 SLEEPO IASLEEP 69 56 14 15 1 57 61 66 70 72 73 74 77 83 84 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPO0 RDCLK TDCLK XTCLK TXD RLSD RI RXD 82 8 12 64 13 11 78 67 SERIAL DTE INTERFACE NC NC NC NC NC NC NC NC NC NC NC NC NC 1154F5 3 MDP HIS 100PQFP 5V 58 71 IA2CLK VGG MCU R...

Page 83: ... 96 98 100 90 47 79 48 50 45 86 37 87 36 88 49 VDD VDD VDD ADVDD VSS VSS VSS VSS VSS VSS ADVSS ADVSS 6 58 77 46 21 43 66 80 81 97 16 30 5V 0 1 10 100 SR4OUT SIN SR3IN SOUT IACLK MCLK IA1CLK ICLK SA1CLK FSYNC SR1IO CTRLSIN D0 D1 D2 D3 D4 D5 D6 D7 RS0 RS1 RS2 RS3 RS4 READ WRITE CS IRQ 14 13 12 11 10 9 8 7 5 4 3 2 1 53 15 52 68 MCU EXTERNAL BUS RESET IARESET SLEEPO REFCNTL 72 44 71 40 TELEPHONE AUDIO...

Page 84: ...RC56D RC336D and RC144D Modem Device Sets Designer s Guide 5 16 Conexant 1154 This page is intentionally blank ...

Page 85: ... 0 65 BSC 0 45 0 19 0 1 MAX 0 0020 0 6673 0 0287 0 0098 0 0051 A A1 A2 D D1 D2 L L1 e b c Coplanarity Min Max Min Max Inches Dim Ref 80 PIN PQFP GP00 D227 Metric values millimeters should be used for PCB layout English values inches are converted from metric values and may include round off errors 0 0945 MAX 0 0138 0 0787 REF 0 6870 0 5512 REF 0 4862 REF 0 0406 0 0630 REF 0 0256 BSC 0 0177 0 0075 ...

Page 86: ...EF 0 65 BSC 0 45 0 19 0 10 MAX 0 0020 0 9035 0 6673 0 0287 0 0098 0 0051 A A1 A2 D D1 D2 E E1 E2 L L1 e b c Coplanarity Min Max Min Max Inches Dim Ref 100 PIN PQFP GP00 D234 Metric values millimeters should be used for PCB layout English values inches are converted from metric values and may include round off errors 0 0945 MAX 0 0138 0 0787 REF 0 9232 0 7874 REF 0 7421 REF 0 6870 0 5512 REF 0 4862...

Page 87: ...INSIDE BACK COVER NOTES ...

Page 88: ...ralia Phone 61 2 9869 4088 Fax 61 2 9869 4077 China Phone 86 2 6361 2515 Fax 86 2 6361 2516 Hong Kong Phone 852 2827 0181 Fax 852 2827 6488 India Phone 91 11 692 4780 Fax 91 11 692 4712 Korea Phone 82 2 565 2880 Fax 82 2 565 1440 Europe Headquarters Conexant Systems France Les Taissounieres B1 1680 Route des Dolines BP 283 06905 Sophia Antipolis Cedex France Phone 33 4 93 00 33 35 Fax 33 4 93 00 3...

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