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Fusion 878A

3.0 Electrical Interfaces

PCI Video Decoder

3.4 I

2

C Interface

100600B

Conexant

3-21

3.4 I

2

C Interface

The I

2

C bus is a two-wire serial interface. Serial clock and data lines, SCL, and

SDA transfer data between the bus master and the slave device. The I

2

C bus

within the Fusion 878A supports repeated starts, up to 396.8 kHz timing, and
multi-byte sequential transactions. The

I2CRATE

signal specifies either

99.2 kHz

or 396.8 kHz timing rate.

If the PCI clock runs at less than the maximum rate,

these rates will slow down proportionately. For details on the I

2

C register, see

0x110—I2C Data/Control Register

.

The relationship between SCL and SDA is decoded to provide both a start and

stop condition on the bus. To initiate a transfer on the I

2

C bus, the master must

transmit a start pulse to the slave device. This is accomplished by taking the SDA
line low while the SCL line is held high. The master should generate a start pulse
only at the beginning of the cycle, or after the transfer of a data byte to or from the
slave. To terminate a transfer, the master must take the SDA line high while the
SCL line is held high. The master may issue a stop pulse at any time during an
I

2

C cycle. Since the I

2

C bus interprets any transition on the SDA line during the

high phase of the SCL line as a start or stop pulse, care must be taken to ensure
that data is stable during the high phase of the clock. This is illustrated in

An I

2

C write transaction consists of sending a START signal, 2 or 3 bytes of

data (checking for a receiver acknowledge after each byte), and a STOP signal.
The write data is supplied from a 24-bit register with bytes I2CDB0, I2CDB1,
and I2CDB2. This 24-bit register is shifted left to provide data serially, with the
MSB as the first bit. An I

2

C write occurs when the R/W bit in the I2CDB0[0] is

set to a logical low. The system driver can write 2 or 3 bytes of data by selecting
the appropriate value for I2CW3BRA bit.

An I

2

C read transaction consists of sending a START signal, 1 byte of data

(checking for a receiver acknowledge), reading 1 data byte from the slave,
sending the master NACK, and sending the STOP signal. The data read is shifted
into the I2CDB2 register. An I

2

C read occurs when the R/W bit in the I2CDB0[0]

is set to a logical 1, illustrated in

.

When the read or write operation is completed, the Fusion 878A sends an

interrupt over the PCI bus to the host controller. The status bit RACK will
indicate if the operation completed successfully with the correct number of slave
acknowledges.

Figure 3-14. The Relationship Between SCL and SDA

Start

Stop

SDA

SCL

879A_045

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104
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106
107
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Summary of Contents for Fusion 878A

Page 1: ...get Initiator Target Initiator Audio Stream Format Audio FIFO DMA Controller DMA Controller Video FIFO Pixel Format Conversion 879A_001 I2S dig audio Decimation LPF Distinguishing Features NTSC PAL SECAM video decoding Supports capture resolutions up to 768 x 576 full PAL On chip PCI bus mastering and bridge functionality Supports HDTV audio MPEG2 transport data across PCI bus High speed serial po...

Page 2: ...nt products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale Conexant the Conexant symbol and What s Next in Communications Technologies are trademarks of Conexant Systems Inc Product names or services listed in this publication are for identification purposes only and may be trademarks or registered...

Page 3: ...Audio DMA Channels 1 5 1 2 7 Data Transport Engine 1 5 1 2 8 PCI Bus Interface 1 6 1 2 9 UltraLock 1 6 1 2 10 Scaling and Cropping 1 6 1 2 11 Input Interface 1 6 1 2 12 GPIO Port 1 7 1 2 13 Vertical Blanking Interval Data Capture 1 7 1 2 14 I2 C Interface 1 7 1 2 15 HDTV Support 1 7 1 3 Pin Descriptions 1 8 2 0 Functional Description 2 1 2 1 UltraLockTM Functionality 2 1 2 1 1 The Challenge 2 1 2 ...

Page 4: ...trol 2 22 2 7 Low Color Detection and Removal 2 22 2 8 Coring 2 23 2 9 VBI Data Output Interface 2 24 2 9 1 VBI Line Output Mode 2 25 2 10 Video Data Format Conversion 2 27 2 10 1 Pixel Data Path 2 27 2 10 2 Video Control Code Status Data 2 27 2 10 3 YCrCb to RGB Conversion 2 30 2 10 4 Gamma Correction Removal 2 30 2 10 5 YCrCb Sub sampling 2 30 2 10 6 Byte Swapping 2 31 2 11 Video and Control Dat...

Page 5: ...7 2 18 6 Data Packet Mode 2 58 2 18 7 Audio Data Formats 2 59 2 18 8 Audio Dropout Detection 2 59 2 19 Digital Television Support 2 60 3 0 Electrical Interfaces 3 1 3 1 Input Interface 3 1 3 1 1 Analog Signal Selection 3 1 3 1 2 Multiplexer Considerations 3 2 3 1 3 Flash A D Converters 3 3 3 1 4 A D Clamping 3 3 3 1 5 Power up Operation 3 3 3 1 6 Automatic Gain Controls 3 3 3 1 7 Crystal Inputs an...

Page 6: ...s 4 1 4 1 Layout Considerations 4 1 4 1 1 Capacitors 4 1 4 1 2 Components 4 2 4 2 Split Planes and Voltage Regulators 4 3 4 3 Latchup Avoidance 4 4 5 0 Control Register Definitions Function 0 5 1 5 1 PCI Configuration Space 5 1 5 2 PCI Configuration Registers Header 5 3 0x00 Vendor and Device ID Register 5 3 0x04 Command and Status Register 5 3 0x08 Revision ID and Class Code Register 5 4 0x0C Hea...

Page 7: ...ROL 0x0AC Odd Field O_CONTROL 5 14 0x030 Luma Gain Register Lower Byte CONTRAST_LO 5 15 0x034 Chroma U Gain Register Lower Byte SAT_U_LO 5 16 0x038 Chroma V Gain Register Lower Byte SAT_V_LO 5 17 0x03C Hue Control Register HUE 5 18 SC Loop Control Register 5 19 0x040 Even Field E_SCLOOP 0x0C0 Odd Field O_SCLOOP 5 19 0x044 White Crush Up Register WC_UP 5 20 0x048 Output Format Register OFORM 5 20 V...

Page 8: ...egister GPIO_DATA 5 36 6 0 Control Register Definitions Function 1 6 1 6 1 PCI Configuration Space 6 1 6 2 PCI Configuration Registers Header 6 3 0x00 Vendor and Device ID Register 6 3 0x04 Command and Status Register 6 3 0x08 Revision ID and Class Code Register 6 4 0x0C Header Type Register 6 4 0x0C Latency Timer Register 6 4 0x10 Base Address 0 Register 6 4 0x2C Subsystem ID and Subsystem Vendor...

Page 9: ...e 2 10 Peaking Filters 2 11 Figure 2 11 Luma Peaking Filters with 2x Oversampling Filter and Luma Notch 2 12 Figure 2 12 Effect of the Cropping and Active Registers 2 17 Figure 2 13 Regions of the Video Signal 2 18 Figure 2 14 Coring Map 2 23 Figure 2 15 Regions of the NTSC Video Frame 2 24 Figure 2 16 Regions of the PAL Video Frame Fields 1 2 5 and 6 2 24 Figure 2 17 VBI Timing 2 25 Figure 2 18 V...

Page 10: ...o Digital Input Port 3 19 Figure 3 13 GPIO Timing Diagram 3 20 Figure 3 14 The Relationship Between SCL and SDA 3 21 Figure 3 15 I2 C Typical Protocol Diagram 3 22 Figure 3 16 Instruction Register 3 30 Figure 4 1 Optional Regulatory Circuitry 4 4 Figure 5 1 Function 0 PCI Configuration Space Header 5 2 Figure 6 1 Function 1 PCI Configuration Space Header 6 2 Figure 7 1 Clock Timing Diagram 7 4 Fig...

Page 11: ... Map 2 54 Table 2 14 Audio Data Formats 2 59 Table 3 1 Recommended Crystals 3 5 Table 3 2 SPI Input GPIO Signals 3 12 Table 3 3 SPI GPIO Output Signals 3 14 Table 3 4 GPIO SPI Mode Timing Parameters 3 17 Table 3 5 Pin Definition of GPIO Port When Using Digital Video In Mode 3 18 Table 3 6 External EEPROM Memory Map 3 23 Table 3 7 EEPROM Upload Sequence 3 24 Table 3 8 VPD Read Sequence 3 26 Table 3...

Page 12: ...List of Tables Fusion 878A PCI Video Decoder xiv Conexant 100600B ...

Page 13: ...rious audio capture capabilities The main features of the Bt848A are NTSC PAL SECAM video decoding multiple YCrCb and RGB pixel formats supported on the output vertical blanking interval VBI data capture for closed captioning teletext and intercast data decoding The complete set of video and audio capture features are documented in this data sheet Table 1 1 indicates which audio capture features a...

Page 14: ...er Analog Video Video Data Format Converter Local Registers Wr Instr Data Rd PCI Bus DMA Controller PCI Initiator Instruction Queue Address Generator FIFO Data MUX PCI Arbiter Audio Decoder FIFO 35x36 Analog Audio Digital Audio AD MUX PCI Target Controller Local Registers Wr Instr Data Rd Interrupts PCI Target Controller Interrupts Digital Video I2C 879A_002 Parity Generator AD MUX Parity Generato...

Page 15: ...ite S Video Y S Video C CIN AGCCAP REFP XTO XTI STV TV Audio SFM Radio Audio SML Mic or Line Level Audio ADATA ALRCK ASCLK Digital Audio I 2 S Y A D C A D AGC Clocking Audio A D Audio Processing Digital Audio Packetizer Oversampling Low Pass Filter Y C Separation Chroma Demod Hue Saturation and Brightness Adjust Horizontal and Vertical Filtering and Scaling Video Data Format Converter Audio FIFO 8...

Page 16: ...ds may be interlaced into memory or sent to separate field buffers 1 2 2 Audio Capture The Fusion 878A can also capture the broadcast audio spectrum over the PCI bus This enables system solutions without the use of an analog audio cable In addition the audio capture can be used to implement microphone audio capture for complete videoconferencing applications 1 2 3 Analog Video and Digital Camera C...

Page 17: ...ta and video RISC instructions Since the audio data path operates in continuous transfer mode no sync gaps both the analog and the digital audio inputs can be used for other data capture applications The analog input offers 360 kHz usable BW at 8 effective bits or 100 kHz usable BW at 12 effective bits The digital input offers up to 20 Mbps for the parallel mode and 40 Mbps for the serial mode The...

Page 18: ...raLock can recognize unstable signals caused by VCR head switches or any other deviation and adapt the locking mechanism to accommodate the source UltraLock uses nonlinear techniques that are difficult if not impossible to implement in genlock systems And unlike linear techniques it adapts the locking mechanism automatically 1 2 10 Scaling and Cropping The Fusion 878A can reduce the video image si...

Page 19: ...sion 878A supports a VBI Frame Output Mode in which every line in the video frame istreated as if it were a VBI line This mode of operation is designed for use with still frame capture processing applications 1 2 14 I2 C Interface The Fusion 878As I2C interface supports both 99 2 kHz timing transactions and 396 8 kHz repeated start multi byte sequential transactions As an I2 C master Fusion 878A c...

Page 20: ...84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VDD GNT REQ AD 31 AD 30 AD 29 AD 28 AD 27 AD 26 AD 25 AD 24 CBE 3 IDSEL AD 23 AD 22 AD 21 AD 20 AD 19 VDD GND AD 18 AD 17 AD 16 CBE 2 FRAME IRDY TRDY DEVSEL STOP PERR SERR PAR GND RST INTA TDI TDO TMS TCK TRST MUX3 AGND MUX2 MUX1 VAA MUX0 AGND REFP AGCCAP VAA CIN AGND VCCAP RBIAS VCOMO VCOMI VRXP VRXN VBB STV BGND SFM BGND CBE 1 AD 15 AD ...

Page 21: ...and memory operations During data phases AD 7 0 contains the least significant byte and AD 31 24 contains the most significant byte Read data is stable and valid when TRDY is asserted and write data is stable and valid when IRDY is asserted Data is transferred during the clocks when both TRDY and IRDY are asserted 12 24 33 45 CBE 3 0 I O Bus Command Byte Enable These three state bidirectional I O ...

Page 22: ...indicates when the target is presenting data During a write TRDY indicates when the target is ready to accept the data Wait cycles are inserted until both IRDY and TRDY are asserted together 29 STOP I O Stop This sustained three state signal indicates the target is requesting the master to stop the current transaction 30 PERR I O Parity Error Report data parity error 31 SERR O System Error Report ...

Page 23: ...1 analog multiplexer Unused inputs should be tied to AGND The output of the MUX is direct coupled to Y A D 112 REFP A The top of the reference ladder for the video A Ds Connect to a 0 1 µF decoupling capacitor to AGND 111 AGCCAP A The AGC time constant control capacitor node Must be connected to a 0 1µF capacitor to AGND 109 CIN I Analog chroma input to the C A D TV Radio Audio Input Signals 10 Pi...

Page 24: ...GND 110 VAA A Charge pump power supply and C video A D power Connect to analog power VAA and a 0 1µF decoupling capacitor to AGND 113 AGND A Charge pump ground return 115 VAA A Y video A D power Connect to analog power VAA and a 0 1µF decoupling capacitor to AGND 117 VAA A Y video A D power Connect to analog power VAA and a 0 1µF decoupling capacitor to AGND 119 AGND A Y video A D ground Connect t...

Page 25: ...ine is always greater than the number of samples per line required by the particular video format the number of acquired samples can be reduced to fit the required number of pixels per line The Fusion 878A requires an 8 Fsc 28 63636 MHz for NTSC and 35 46895 MHz for PAL reference time source The 8 Fsc clock signal or CLK x 2 is divided down to CLK x 1 internally 14 31818 MHz for NTSC and 17 73 MHz...

Page 26: ...sed to extract any programmable number of pixels from the original video stream as long as the sum of the nominal pixel line length 910 for NTSC and 1 135 for PAL SECAM and the worst case line length validation from nominal in the active region is greater than or equal to the required number of output pixels per line i e NOTE With stable inputs UltraLock guarantees the time between the falling edg...

Page 27: ...South Africa PAL M 525 60 3 58 MHz Brazil PAL NC 625 50 3 58 MHz Argentina PAL N 625 50 3 58 MHz Paraguay Uruguay SECAM 625 50 4 406 MHz 4 250 MHz Eastern Europe France Middle East NOTE S 1 NTSC Japan has 0 IRE setup Table 2 2 Register Values for Square Pixel Video Input Formats Register Bit NTSC M NTSC Japan PAL B D G H I PAL M PAL N PAL N Combination SECAM IFORM 0x01 FORMAT 2 0 001 010 011 100 1...

Page 28: ...he Y C separation and chroma demodulation illustrated in Figure 2 2 the Fusion 878A also supports chrominance comb filtering as an optional filtering stage after chroma demodulation The chroma demodulation generates baseband I and Q NTSC or U and V PAL SECAM color difference signals For S Video operation the digitized luma data bypasses the Y C separation block completely and the digitized chromin...

Page 29: ...ion 100600B Conexant 2 5 Figure 2 3 Y C Separation Filter Responses NTSC PAL SECAM NTSC PAL SECAM Luma Notch Filter Frequency Responses for NTSC and PAL SECAM Chroma Band Pass Filter Frequency Responses for NTSC and PAL SECAM 879A_007 Amplitude in dB 20 log10 ampl Frequency in MHz Frequency in MHz ...

Page 30: ...rithm Chrominance 1 2 1 2 Z 1 Luminance C DZ 1 Vertical Scaler Luminance A BZ 1 CZ 2 DZ 3 EZ 4 FZ 5 Chrominance G HZ 1 Horizontal Scaler 6 Tap 32 Phase Interpolation On chip Memory and Horizontal Scaling On chip Memory and Chroma Comb Low Pass Filter Y Y C C Optional Horizontal Vertical Scaling Luma Comb Chroma Comb 3 MHz 1 4 1 2Z 1 1Z 2 1 8 1 3Z 1 3Z 2 1Z 3 1 16 1 4Z 1 6Z 2 4Z 3 Z 4 Vertical Filt...

Page 31: ...yet maintain proper field alignment This mode is selected by setting VSFLDALIGN and resetting the INT bit to non interlaced Vertical Scaling mode 2 4 1 3 Luminance Scaling Horizontal Scaling The first stage in horizontal luminance scaling is an optional pre filter which provides the capability to reduce anti aliasing artifacts It is generally desirable to limit the bandwidth of the luminance spect...

Page 32: ... NTSC PAL SECAM ICON QCIF CIF ICON QCIF CIF Amplitude in dB 20 log10 ampl Amplitude in dB 20 log10 ampl Frequency in MHz Frequency in MHz 879A_009 Figure 2 6 Combined Luma Notch 2x Oversampling and Optional Low Pass Filter Response NTSC ICON QCIF CIF ICON QCIF CIF Pass Band Full Spectrum Amplitude in dB 20 log10 ampl Amplitude in dB 20 log10 ampl Frequency in MHz Frequency in MHz 879A_010 ...

Page 33: ...h the horizontal scale factor in order to ensure the needed data fits in the internal FIFO see the VFILT bits in the VTC register for limitations As the scaling ratio is increased the number of taps available for vertical scaling increases In addition to low pass filtering vertical interpolation is also employed to minimize artifacts when scaling to non integer scaling ratios Figure 2 7 Combined L...

Page 34: ...fferent peaking levels by programming the PEAK bit and HFILT bits in the SCLOOP register The filters are illustrated in Figure 2 10 and Figure 2 11 For more information refer to SC Loop Control Register Figure 2 9 Frequency Responses for the Four Optional Vertical Luma Low Pass Filters 2 tap 3 tap 4 tap 5 tap Amplitude in dB 20 log10 ampl 879A_013 Frequency Sampling_Frequency ...

Page 35: ...d Temporal Decimation 100600B Conexant 2 11 Figure 2 10 Peaking Filters HFILT 01 HFILT 10 HFILT 11 HFILT 00 Amplitude in dB 20 log10 ampl 879A_014 Frequency in MHz HFILT 01 HFILT 11 HFILT 10 HFILT 00 Enhanced Resolution of Passband Amplitude in dB 20 log10 ampl 879A_015 Frequency in MHz ...

Page 36: ... 12 Conexant 100600B Figure 2 11 Luma Peaking Filters with 2x Oversampling Filter and Luma Notch 1 of 2 HFILT 10 HFILT 01 HFILT 11 HFILT 00 HFILT 01 HFILT 11 HFILT 10 HFILT 00 Enhanced Resolution of Passband 879A_016 Amplitude in dB 20 log10 ampl Amplitude in dB 20 log10 ampl Frequency in MHz Frequency in MHz ...

Page 37: ... fCLK x 1 4 Fsc This register is the control for scaling the video to the desired size For example square pixel NTSC requires 780 samples per line while CCIR 601 requires 858 samples per line HSCALE_HI and HSCALE_LO are two 8 bit registers that when concatenated form the 16 bit HSCALE register The method below uses pixel ratios to determine the scaling ratio The following formula should be used to...

Page 38: ...d using the full line length ratio The Vertical Scaling Ratio Register VSCALE VSCALE is programmed with the vertical scaling ratio It defines the number of vertical lines output by the Fusion 878A The following formula should be used to determine the value to be entered into this 13 bit register The loaded value is a two s complement negative value For example to scale PAL SECAM input to square pi...

Page 39: ...CALE_HI newVscaleMSByte send the new VscaleLSByte to the VSCALE_LO reg WriteToFusion878A VSCALE_LO BYTE VSCALE If your target machine has sufficient memory to statically store the scaling values locally the READ operation can be eliminated NOTE When scaling below CIF resolution it may be useful to use a single field as opposed to using both fields Using a single field will ensure there are no inte...

Page 40: ...in Figure 2 12 Table 2 3 Scaling Ratios for Popular Formats Using Frequency Values Scaling Ratio Format Total Resolution 1 Output Resolution Active Pixels HSCALE Register Values VSCALE Register Values Use Both Fields Single Field Full Resolution 1 1 NTSC SQ Pixel NTSC CCIR601 PAL CCIR 601 PAL SQ Pixel 780x525 858x525 864x625 944x625 640x480 720x480 720x576 768x576 0x02AA 0x00F8 0x0504 0x033C 0x000...

Page 41: ...ffect of the Cropping and Active Registers Beginning of a New Frame Beginning of a New Line Video frame Horizontally Active Horizontally Inactive Vertically Vertically Video frame Horizontally Horizontally Inactive Vertically Vertically Cropped image Cropped image scaled to 1 2 size Active Inactive Active Inactive Active HRESET VRESET 879A_017 ...

Page 42: ... HACTIVE signal is high after the HACTIVE signal goes high The register value is programmed with respect to the scaled frequency clock The video line can be considered a combination of three components 1 Back porch and Sync defined by HDELAY 2 Active Video defined by HACTIVE 3 Front Porch total scaled pixels HDELAY through HACTIVE For uncropped images the square pixel values for these components a...

Page 43: ...not used 2 4 3 Temporal Decimation Temporal decimation provides a solution for video synchronization during periods when full frame rate cannot be supported due to bandwidth and system restrictions For example when capturing live video for storage system limitations such as hard disk transfer rates or system bus bandwidth may limit the frame capture rate If these restrictions limit the frame rate ...

Page 44: ...DEC register can be programmed to choose whether the decimation starts with an odd field or an even field If the FLDALIGN bit is set to logical 0 the first field dropped during the decimation process will be an odd field Conversely setting the FLDALIGN bit to logical 1 causes the even field to be dropped first in the decimation process TDEC 0x9E Decimation is performed by fields Thirty fields are ...

Page 45: ...gister The Contrast Adjust Register CONTRAST also called the luma gain provides the ability to change the contrast from approximately 0 to 200 of the original value The decoded luma value is multiplied by the 9 bit coefficient loaded into this register 2 5 3 The Saturation Adjust Registers The Saturation Adjust Registers SAT_U SAT_V are additional color adjustment registers It is a multiplicative ...

Page 46: ...aturation adjust value for a total chrominance gain range of 0 2 times the original signal Automatic chrominance gain control may be disabled 2 7 Low Color Detection and Removal If a color burst of 25 percent NTSC or 35 percent PAL SECAM or less of the nominal amplitude is detected for 127 consecutive scan lines the color difference signals U and V are set to 0 When the low color detection is acti...

Page 47: ...images and turning them into black the image appears clearer to the eye Four coring values can be selected 0 8 16 or 32 above black If the total luminance level is below the selected limit the luminance signal is truncated to the black value If the luma range is limited i e black is 16 then the coring circuitry automatically takes this into account and references the appropriate value for black Co...

Page 48: ...273 through 283 These regions between the vertical synchronization region and the video picture region are referred to as the VBI portion of the video signal Figure 2 16 illustrates the PAL video frame Figure 2 15 Regions of the NTSC Video Frame Figure 2 16 Regions of the PAL Video Frame Fields 1 2 5 and 6 Lines 1 9 Lines 10 20 Lines 21 263 Lines 264 272 Lines 273 283 Lines 284 525 Vertical Blanki...

Page 49: ...it is enabled for the even field and CAPTURE_VBI_ODD register bit is enabled for the odd field The VBI data is sampled at a rate of 8 Fsc and is stored in the FIFO as a sequence of 8 bit samples Line mode VBI data starts horizontally beginning at VBI_HDELAY pixels from the trailing edge of HRESET and ending after the VBI_PKT number of DWORDs Line mode VBI data starts vertically beginning at the fi...

Page 50: ...650 256 DWORDs per field The VBI frame capture region can be extended to include the 10 lines prior to the default VACTIVE region by setting the EXT_FRAME register bit VDELAY must also be set to its minimum value of 2 The extended DWORD block size is 450 DWORD blocks for NTSC and 674 DWORD blocks for PAL The VBI frame data capture occurs during the even field when the CAPTURE_EVEN register bit is ...

Page 51: ...2 and vertically sub sampled to YUV12 format The vertical sub sampling is achieved via the appropriate DMA instructions see Section 2 12 Fusion 878A also offers a Y8 color format in which the chroma component of the packed 4 2 2 data is stripped and the luma component is packed into 8 bits This format is otherwise known as gray scale Table 2 5 lists the various color formats supported by the Fusio...

Page 52: ...roma and Pack Luma Sub Sample Chroma Packed to Planar Conversion Internal Control Signals from Bt879 Family Video Decoder Video Control Code Generator Packed to Planar Conversion Status 3 0 FIFO Write Signals FIFO Write Clock To FIFO FI 35 32 Packed 4 1 1 BtYUV Planar 4 1 1 Planar 4 1 1 Planar 4 2 2 Planar 4 2 2 Planar YUV12 Planar YUV9 Vertical Sub Sample Chroma DMA Controller From FIFO Y8 Gray S...

Page 53: ...dw1 Y3 Cr4 Y2 Cb4 dw2 Y7 Y6 Y5 Y4 Y8 Gray Scale dw0 Y3 Y2 Y1 Y0 8 Bit Dithered dw0 B3 B2 B1 B0 VBI Data dw0 D3 D2 D1 D0 YCrCb 4 2 2 Planar dw0 FIFO1 Y3 Y2 Y1 Y0 dw1 FIFO1 Y7 Y6 Y5 Y4 dw0 FIFO2 Cb6 Cb4 Cb2 Cb0 dw0 FIFO3 Cr6 Cr4 Cr2 Cr0 YUV12 Planar Vertically sub sampled to 4 2 2 by the DMA controller YCrCb 4 1 1 Planar dw0 FIFO1 Y3 Y2 Y1 Y0 dw1 FIFO1 Y7 Y6 Y5 Y4 dw2 FIFO1 Y11 Y10 Y9 Y8 dw3 FIFO1 Y...

Page 54: ...oval Fusion 878A provides gamma correction removal capability The available gamma values are NTSC RGBout RGBin2 2 PAL RGBout RGBin2 8 Gamma correction removal capability is not programmable on a field basis Furthermore gamma correction removal is not available when YCrCb data is output 2 10 5 YCrCb Sub sampling The 4 2 2 data stream is horizontally sub sampled to 4 1 1 using the following equation...

Page 55: ...port Macintosh big endian color data formats The pixel DWORD PD 31 0 maps onto the FIFO input FI 31 0 The byte swap MUX remaps the data bytes but byte lane 0 or bits 7 0 will still be considered the first byte of the scan line See Table 2 6 Table 2 6 Byte Swapping Map Word Swap 0 1 Byte Swap 0 1 0 1 FIFO Inputs Outputs of FIFO Data Formatter FI 31 24 PD 31 24 PD 23 16 PD 15 8 PD 7 0 FI 23 16 PD 23...

Page 56: ... Each of the 140 FIFO data words provide for one DWORD of pixel data and four bits of video control code status This is illustrated in Figure 2 20 The FIFOs are large enough to support efficient size burst transfers 16 to 32 data phases in planar as well as packed mode Figure 2 20 Data FIFO Block Diagram FIFO1 70 x 36 FIFO2 35 x 36 FIFO3 35 x 36 Y Cr Cb FIFO Write Signals From VDFC FIFO Enable Sig...

Page 57: ...ure of a field is asynchronously enabled The mode status codes are always stored in planar format FIFO1 receives two copies of the status code while FIFO2 and FIFO3 each receive one copy The SOL code is packed in the FIFO with the first valid pixel data byte which is the first pixel DWORD for the scan line The EOL code is packed in the FIFO with the last valid pixel data byte which is the last DWO...

Page 58: ...oncurrently and independently In packed mode however the three FIFOs operate in a merged mode to provide the maximum size buffer FSIZE1 2 and 3 indicate the physical size of each FIFO FSIZET represents the total buffer size when the FIFOs work together in packed mode 2 11 4 FIFO Input Output Rates The input and output ports of the Fusion 878A s FIFO can operate simultaneously and are asynchronous ...

Page 59: ...27 RGB16 YCrCb 4 2 2 41 YCrCb 4 1 1 55 Y8 8 bit dithered VBI 83 PAL SECAM 25 fps 768 x 576 RGB32 8 RGB24 11 RGB16 YCrCb 4 2 2 17 YCrCb 4 1 1 23 Y8 8 bit dithered VBI 34 PAL SECAM 25 fps 384 x 288 RGB32 17 RGB24 23 RGB16 YCrCb 4 2 2 34 YCrCb 4 1 1 46 Y8 8 bit dithered VBI 69 Effective Rate M Pixels Sec NTSC 640 x 480 12 27 NTSC 320 x 240 6 14 NTSC 720 x 480 13 50 PAL 768 x 576 14 75 PAL 384 x 288 7...

Page 60: ... image data Line 21 closed captioning data Line 15 teletext data The Fusion 878A DMA can concurrently support a display memory target for the even field image and three separate system memory targets for the odd field image line 21 data and line 15 data images respectively The Fusion 878A device driver software creates a RISC program which runs the DMA controller The RISC program resides in host s...

Page 61: ... Program Setup and Synchronization There are two independent sets of RISC instructions in the host memory one for the odd field and the other for the even field The first field begins with a synchronization instruction See SYNC in Table 2 10 indicating packed or planar data from the FIFO STATUS 3 0 FM1 or FM3 The first field ends with a SYNC instruction indicating an even or an odd field to follow...

Page 62: ...packed mode RISC instructions WRITE WRITEC SKIP SYNC and JUMP that control the data stored in the FIFO Three additional planar mode instructions exist which replace the simple packed mode WRITE SKIP instructions Instruction details are listed in Table 2 10 The DMA controller switches from packed mode to planar mode or vice versa based on the status codes flowing through the FIFOs along with the pi...

Page 63: ...Byte enables 23 16 Reset Set RISC_STATUS 24 IRQ 25 Reserved 26 EOL 27 SOL 31 28 Opcode DWORD1 11 0 Byte count 2 Byte transfer count from FIFO2 27 16 Byte count 3 Byte transfer count from FIFO3 DWORD2 31 0 32 bit target address Byte address for Y data from FIFO1 DWORD3 31 0 32 bit target address Byte address for Cb data from FIFO2 DWORD4 31 0 32 bit target address Byte address for Cr data from FIFO...

Page 64: ...nsfer count from FIFO1 15 12 Byte enables 23 16 Reset Set RISC_STATUS 24 IRQ 25 Reserved 26 EOL 27 SOL 31 28 Opcode DWORD1 11 0 Byte count 2 Byte skip count from FIFO2 27 16 Byte count 3 Byte skip count from FIFO3 DWORD2 31 0 32 bit target address Byte address for Y data from FIFO1 WRITEC 0101 1 Write packed mode pixels to memory from the FIFO continuing from the current target address DWORD0 11 0...

Page 65: ...23 16 Reset Set RISC_STATUS 24 IRQ 25 Reserved 26 EOL 27 SOL 31 28 Opcode SKIP123 1010 2 Skip pixels in planar mode by discarding byte count 1 of bytes from the FIFO1 and byte count 2 from FIFO2 and FIFO3 This may start and stop in the middle of a DWORD DWORD0 11 0 Byte Count 1 15 12 Reserved 23 16 Reset Set RISC_STATUS 24 IRQ 25 Reserved 26 EOL 27 SOL 31 28 Opcode DWORD1 11 0 Byte count 2 27 16 B...

Page 66: ...ess the line both SOL and EOL bits will be set WRITE WRITEC and SKIP control the processing of active pixel data stored in the FIFO These three instructions alone control the sequence of packed mode data written to target memory on a byte resolution basis The WRITEC instruction does not supply a target address Instead it relies on continuing from the current DMA pointer contained in the target add...

Page 67: ...o applies to SYNC instructions specifying unused or reserved status codes Detecting RISC instruction errors is useful for detecting software errors in programming or ensuring that the DMA controller is following a valid RISC sequence In other words it ensures that the program counter is not pointing to the wrong location All unused reserved bits in the instruction DWORDs must be set to 0 2 12 4 Co...

Page 68: ...ISC instructions can be flushed sooner for every scan line Otherwise the DMA controller may have to wait for many scan lines before the required number of DWORDs are present in the FIFO especially when capturing highly scaled down images There may be several horizontal lines before another DWORD enters the FIFO The FIFO trigger point is ignored by the DMA controller during all SKIP instructions In...

Page 69: ...on 878A monitors the FIFO Almost Full FAFULL counters The difference between FFULL and FAFULL provides the necessary headroom to handle target latency Before the DMA controller executes the address phase of a PCI write transaction to process a WRITE instruction the FIFO count value must be below the FAFULL level At all other times the FIFOs must be maintained below the FFULL level The FIFO counter...

Page 70: ... the EOL control code from the FIFO earlier than expected The DMA controller then aborts the rest of the RISC instructions until it detects the EOL control code from the RISC program If the FIFO contains a longer video line than expected by the RISC instruction the DMA controller will not detect the EOL control code from the FIFO at the expected time The DMA controller will continue reading the FI...

Page 71: ...The target address used is a byte lane offset relative address as opposed to an absolute byte address So if multiple WRITE instructions are used per video line each would have the same byte offset no matter which byte lane SKIP starts or stops at Formerly reserved bits 13 12 of the SKIP instruction must contain the byte offset two LSB s of the target address if they are using byte aligned addresse...

Page 72: ...o the bus access latency that the audio PCI FIFO can tolerate 2 14 2 430FX Compatibility Mode When using the 430FX PCI the following rules will ensure compatibility 1 De assert REQ at the same time as asserting FRAME 2 Do not reassert REQ to request another bus transaction until after finishing the previous transaction Since individual bus masters do not have direct control of REQ a simple logical...

Page 73: ...bility when using PCs with these PCI controllers the EN_VSFX bit must be enabled refer to 0x40 Device Control Register When in this mode the arbiter does not pass GNT to the internal functions unless REQ is asserted This prevents a bus transaction from starting the same cycle when GNT is de asserted This also has the side effect of not being able to take advantage of bus parking thus lowering arbi...

Page 74: ...ely 20 kΩ 2 15 2 Input Gain Control The audio frequency AF output level from the TV tuners ranges from 250 mVRMS to 750 mVRMS typically riding on a 2 VDC offset If the A D nominal operating point is 0 5 VRMS 1 414 Vp p then the input gain needs to vary from 3 5 dB to 6 0 dB The input signal is gained in discrete linear steps via A_GAIN 3 0 Table 2 12 shows the calculated gain values The A_GAIN val...

Page 75: ... the pre amp This additional amplification is enabled if A_G2X is set high Thus when A_GAIN equals 3 and A_G2X equals 1 the maximum signal input would be 0 25 VRMS The 6 dB boost is useful for very small input signals 13 2 667 8 52 0 188 0 530 14 2 833 9 05 0 176 0 499 15 3 000 9 54 0 167 0 471 Table 2 12 Gain Control 2 of 2 A_GAIN Input GAIN dB Nominal Input Vrms Vp p ...

Page 76: ...tical to the timing in Digital Audio input mode refer to Figure 3 3 The DA_SCE bit determines whether the data is clocked in on the rising edge or the falling edge of ASCLK When DA_SCE is low default data is clocked in on the rising edge If falling edge clocking is desired DA_SCE must be changed to 1 The DA_MLB bit determines the bit order When DA_MLB is low default the MSB first format is used If...

Page 77: ...ode the DA_APP bit switches the functionality of the ALRCK pin When DA_APP is high use ALRCK to clock in the data on GPIO 23 8 This interface is dubbed asynchronous because the clock is not required to be continuous or fixed rate From the point where it is multiplexed into the Digital Audio Packetizer the GPIO data is treated the same as normal audio data From the Packetizer data goes into a 35 36...

Page 78: ... to the system memory page sizes The FM1 and VRO codes bound a finite number of packets These delimiter codes are useful for providing data delivery checks RISC program loop checks and synchronization The PXV code is used for all valid audio samples between the packetizing codes SOL EOL Both the input and output sides of the FIFO run off the PCI clock 2 18 2 PCI Bus Latency Tolerance for Audio Buf...

Page 79: ...t also be less than the FRCLK rate Since FWCLK FRCLK PCI CLK for this instance the write rate is not an issue The 6 bit DWORD counter indicates the number of DWORDs stored in the FIFO It is cleared when FIFO_ENABLE is reset to 0 Otherwise FIFO_WR cntr and FIFO_RD cntr This counter is part of the DAP block The 6 bit DWORD counter will be available for monitoring on GPIO 13 8 during debug mode simil...

Page 80: ...Packet Data ALP_LEN always controls the proper usage of EOL codes Thus in the case of A D interface where data is presented as 16 bit words an odd number of bytes used for ALP_LEN would cause one byte to be lost since this byte would not be carried into the next line Similarly for the digital audio interface which consists of L R word pairs an ALP_LEN not a multiple of four would cause data to be ...

Page 81: ...eam where the highest ASCLK allowed is 64 x 48 kHz 3 072 MHz ADATA must supply at least 16 bits per left and 16 bits per right audio sample The framing ALRCK clock is a square wave usually aligned with the start of each sample The universal interface can be configured by several register values The bit DA_SCE 0 rising 1 falling chooses the edge of ASCLK used to sample the bit stream on ADATA The b...

Page 82: ...imum data rate allowed is 1 MBps or 8 MHz for ASCLK There is no requirement for the interface signals to be continuous The signal ALRCK is used for byte alignment and packet framing DA_LRD will be used again to delay sampling of the shift register to output packet data bytes DA_LRD ASCLKs after the leading edge of ALRCK indicates the first bit of the first byte Successive bytes are transferred eve...

Page 83: ... 0x808080 it is possible to detect words or bytes of audio not delivered down to a single sample resolution level Enabling DA_LMT will cause the audio DMA to exclude writing 0x8000 words or 0x80 bytes mode determined by DA_SBR to the memory buffer When the DAP detects 0x8000 it replaces this code with 0x8001 while in 16 bit mode The 0x8000 sample is usually not present since it represents the most...

Page 84: ... 2 19 Digital Television Support PCI Video Decoder 2 60 Conexant 100600B 2 19 Digital Television Support Digital television support will be available through upcoming application notes Please contact the local sales office for availability ...

Page 85: ... four composite sources In the second configuration connect three inputs to the composite sources and the other input to the luma component of the S Video connector When an S Video source is input to the Fusion 878A the luma component feeds through the input analog multiplexer and the chroma component feeds directly into the C input pin An automatic gain control circuit enables the Fusion 878A to ...

Page 86: ...ched on a real time pixel by pixel basis Figure 3 1 Typical External Circuitry MUX2 MUX3 CIN REFP 75 Ω AC Coupling Capacitor AGCCAP 75 Ω 0 1 µF MUX1 75 Ω 0 1 µF 75 Ω 0 1 µF 75 Ω 0 1 µF 75 Ω 0 1 µF MUX0 0 1 µF 0 1 µF 0 1 µF 0 1 µF 0 1 µF AGND VAA BGND VCOMO RBIAS VCCAP VCOMI VRXP VRXN 0 1 µF 0 1 µF 0 1 µF 9 53 kΩ 1 VBB 0 1 µF 68 pF 1 0 µF 1 0 µF 1 0 µF STV SFM SML SMXC BGND Video Audio 0 1 µF Termi...

Page 87: ... tip The Y input is always restored to ground while the C input is always restored to REFP 2 3 1 5 Power up Operation Upon power up the status of the Fusion 878A s registers is indeterminate The RST signal must be asserted to set the register bits to their default values Upon reset the Fusion 878A defaults to NTSC M format 3 1 6 Automatic Gain Controls The Fusion 878A controls the voltage for the ...

Page 88: ...ce must be followed 1 Initially TGCKI bits in the TGCTRL register must be programmed for normal operation of the XTAL ports 2 After the PLL registers are programmed the PLOCK bit in the DSTATUS register must be polled until it has been verified that the PLL has attained lock approximately 500 ms 3 At that point the TGCKI bits are set to select operation via the PLL Crystals are specified as follow...

Page 89: ...mental MMD Components Irvine CA Phone 949 753 5888 Fax 949 753 5889 EMail www mmd com info mmdcomp com A30BA3 28 63636 3rd Overtone A30BA1 28 63636 Fundamental General Electronics San Marcos CA Phone 760 591 4170 Fax 760 591 4164 EMail gedlm 4dcomm com Web www gedlm com PKHC49 28 63636 030 005 40R 3rd Overtone PKHC49 U 28 63636 030 005 15R F Fundamental M Tron Industries Yankton SD Phone 605 665 9...

Page 90: ...eo signals do not require additional external filtering After digitalization the samples are digitally low pass filtered and then decimated to 4 Fsc The response of the digital low pass filter is illustrated in Figure 3 3 The digital low pass filter provides the digital bandwidth reduction to limit the video to 6 MHz Figure 3 2 Clock Options CL CL 28 63636 MHz Fundamental Crystal Oscillator 1 MΩ S...

Page 91: ...00600B Conexant 3 7 Figure 3 3 Luma and Chroma 2x Oversampling Filter NTSC PAL SECAM NTSC PAL SECAM Amplitude in dB 20 log10 ampl Amplitude in dB 20 log10 ampl Frequency in MHz Frequency in MHz 0 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 14 16 0 1 2 3 4 5 6 7 0 2 4 6 8 10 879A_034 ...

Page 92: ...pported PCI bus features are 64 bit bus extension I O transactions Special interrupt acknowledge dual address cycles Locked transactions Caching protocol Initiator fast back to back transactions to different targets As a PCI master the Fusion 878A supports agent parking AD 31 0 CBE 3 0 and PAR driven if GNT is asserted and follows an idle cycle regardless of the state of bus master All bus command...

Page 93: ...Controller PCI Initiator PCI Control Signals PCI Config Registers Local Registers Interrupts GPIO I2C Master PCI Target INTA PCI Bus Interface 879A_035 Figure 3 5 PCI Audio Block Diagram FIFO Data FIFO Control Signals Digital Audio CLK DMA Controller PCI Initiator PCI Control Signals PCI Config Registers Local Registers Interrupts Digital Audio Processor PCI Target INTA PCI Bus Interface 879A_036 ...

Page 94: ...The GPIOMODE bits determine the port s mode of operation Each GPIO pin can be individually configured but GPIOMODE affects the entire port 3 3 3 GPIO Normal Mode The Normal mode of the GPIO port can be used to input or output general board level signals to or from the PCI interface in the Fusion 878A The GPIOMODE bits are in the default state of 00 during Normal mode The GPIO port in Normal mode w...

Page 95: ...ontention on the signal Avoid enabling GPOE n when expecting to read an external value on GPIO n Normal mode permits PCI burst transfers by providing a 64 DWORD contiguous address space Only the lower 24 bits of the 32 bit PCI DWORD are sent over the GPIO port An interrupt may be requested through the GPIO 8 pin The GPINTR pin is linked to the Interrupt Status Register within the part and controls...

Page 96: ...tion Pin Number 23 HRESET A 1 to 64 GPCLK long active low pulse It is accepted on the rising edge of GPCLK The falling edge of HRESET indicates the beginning of a new video line 56 22 VRESET A 1 clock to 6 lines long active low pulse It is accepted on the rising edge of GPCLK The falling edge of VRESET indicates the beginning of a new field of video output 57 21 HACTIVE An active high signal that ...

Page 97: ...3 17 VACTIVE An active high signal that indicates the beginning of the active video and is accepted on the rising edge of GPCLK The VACTIVE flag is used to indicate where nonblanking pixels are present 67 16 GROUND 68 15 8 Y 7 0 Digital pins for the luminance component of the video data stream or for 8 bit transfers 69 72 75 78 7 0 CrCb 7 0 Digital pins for the chrominance component of the video d...

Page 98: ...E signal can be adjusted by programming the HDELAY and HACTIVE registers 58 20 DVALID An active high pixel qualifier that indicates whether or not the associated pixel is valid DVALID is independent of the HACTIVE and VACTIVE signals DVALID indicates which pixels are valid DVALID will toggle high outside of the active window indicating a valid pixel outside the programmed active region 59 19 CBFLA...

Page 99: ... 15 Related video timing signals for both fields are illustrated in Figure 3 11 Note that in Fields 1 3 5 and 7 the falling edge of HRESET is two clock cycles ahead of the falling edge of VRESET Figure 3 10 Basic Timing Relationships for SPI Output Mode Y 7 0 CRCB 7 0 DVALID HACTIVE GPCLK CBFLAG 879A_043 ...

Page 100: ...cycles at the beginning of fields 1 3 5 and 7 to facilitate external field generation 2 FIELD transitions with the end of horizontal active video defined by HDELAY and HACTIVE HRESET VRESET HACTIVE FIELD 1 HRESET VRESET HACTIVE FIELD VACTIVE VBISEL VBISEL VACTIVE Beginning of Fields 2 4 6 8 Beginning of Fields 1 3 5 7 VDELAY 2 Scan Lines 2 6 Scan Lines VDELAY 2 Scan Lines 2 6 Scan Lines 879A_042 ...

Page 101: ...able 3 4 GPIO SPI Mode Timing Parameters Parameter Symbol Min Typ Max Units NTSC 4 FSC Rate FS1 14 31746 14 31818 14 31889 MHz PAL 4 FSC Rate FS1 17 73358 17 73447 17 73535 MHz GPCLK Duty Cycle GPCLK falling edge to Data Delay Data Control Setup to GPCLK falling edge Data Control Hold to GPCLK falling edge 4 5 6 45 0 5 5 55 15 ns ns ns GPCLK Input Cycle Time Low Time High Time 7 8 9 56 22 22 10 00...

Page 102: ...two timing reference codes SAV and EAV occur at the start and end of active video respectively These 4 byte codes occur at the outside boundaries of the active video In the active video line 720 pixels correspond to 1440 samples 1448 bytes comprise a video data block one line of video with reference codes The full video line consists of 1716 bytes in 525 line systems and 1728 bytes in 625 line sys...

Page 103: ...M table Place the Timing Generator Video mode into Read Write mode TGC_VM bit in the TGCNTRL register Reset the Timing Generator Address GPC_AR in the TGCNTRL register Write the LSB of the TG_RAM table first The address will be incremented automatically TG_RAM maps may be obtained from your local FAE 5 Set the desired PLL frequency This is not necessary but will provide the correct blue screen out...

Page 104: ...tal Video Input Modes Figure 3 13 illustrates an overview of the GPIO timing for SPI Input and Digital Video Input modes Figure 3 13 GPIO Timing Diagram GPCLK 4 5 6 8 9 7 6 5 SPI Input and Digital Video Input Mode using GPCLK as Input Digital Video Input Mode using GPCLK as Output SPI Output Mode Pixel and Data Pixel and Data Pixel and Data 879A_051 ...

Page 105: ...the I2C bus interprets any transition on the SDA line during the high phase of the SCL line as a start or stop pulse care must be taken to ensure that data is stable during the high phase of the clock This is illustrated in Figure 3 14 An I2 C write transaction consists of sending a START signal 2 or 3 bytes of data checking for a receiver acknowledge after each byte and a STOP signal The write da...

Page 106: ...CDONE interrupt is processed The second and successive register writes will enable 1 byte writes to be transmitted without START and without STOP I2CNOS1B I2CNOSTOP both high The last register write should enable the final STOP to be sent to end the sequential write transaction set The 1 byte write data is sent from I2CDB0 The R W mode was saved from the first register write when the START was tra...

Page 107: ... typically a single 24C02 Re map the 8 bit addressable physical memory space to an 8 bit logical address space by inverting the address A 7 0 and subtracting 4 The 7 bit slave device address is 1010_xxx where the xxx bits are normally used for A 10 8 set to zero The A2 A1 A0 pins on the 24C02 device should be tied low to match Re mapping the address space in this way allows the subsystem IDs to be...

Page 108: ... physical address 0xFC The full read sequence is detailed in Table 3 7 If at any time the slave device issues a NACK because the device is not present the sequence is aborted and the subsystem vendor IDs read 0x00000000 Normally it will take 660 µs to read this DWORD into the PCI configuration register If this register is accessed before it is updated the PCI target will issue a RETRY 3 5 2 2 Regi...

Page 109: ...he VPD Data register and the EEPROM To read information from the EEPROM write a 0 to the VPD flag at the same time you supply the 15 bit address to the VPD address bits of the VPD Capability register The Fusion 878A then sets the VPD flag after it completes reading 4 bytes from the EEPROM returning Address 3 Address 0 little endian format Software should monitor the flag to determine the correct t...

Page 110: ...I2C sequence to write four bytes to the EEPROM assumes VPD address was set to 247 not DWORD aligned Table 3 8 VPD Read Sequence Master Slave Master Comment Control Data Data Control Control START 0xA0 ACK Write ctrl byte with slave chip adr 0xF8 ACK Data bytes base address START 0xA1 ACK Read ctrl byte with slave chip adr 0x ACK VPD 31 24 3 0xF8 0x ACK VPD 23 16 2 0xF9 0x ACK VPD 15 8 1 0xFA 0x NA...

Page 111: ...med into the EEPROM If a slave NACK is received during either page write the sequence is aborted and the flag bit is not reset NOTE The VPD base address used is VPD logical adr 7 8 hFF for the first word page mode write and VPD logical adr 5 XOR 0xFF for the second word page mode write A SW time out on the flag status is the only way to detect an error It takes 4 mS to program the DWORD into the E...

Page 112: ...3cold off by default Each function also supports D3hot independently When placing a function in D3hot the operating system is required to disable I O and memory space as well as bus mastering via the PCI Command register Restoring a function from D3 requires the operating system to re initialize the function Full context must be restored before the function is capable of resuming normal operation ...

Page 113: ...it JTAG is particularly useful for board testers using functional testing methods JTAG consists of five dedicated pins comprising the Test Access Port TAP Test Mode Select TMS Test Clock TCK Test Data Input TDI Test Data Out TDO Test Reset TRST The TRST pin will reset the JTAG controller when pulled low at any time Verification of the integrated circuit and its connection to other modules on the p...

Page 114: ...he Fusion 878A can verify board connectivity at all digital interfaces and pins The instructions listed below are accessible by using a state machine standard to all JTAG controllers Sample Preload Extest ID Code Bypass see Figure 3 16 Refer to the IEEE Std 1149 1 specification for details concerning the Instruction Register and JTAG state machine http standards ieee org Conexant has created a BSD...

Page 115: ...s as close to the Fusion 878A where possible Also whenever possible place traces from all power pins to a bypass capacitor on the component side in addition to any feed through Finally place traces from all ground pins to a bypass capacitor on the component side in addition to any feed through when possible Ensure that there is ample ground plane under the Fusion 878A Make wide paths of copper und...

Page 116: ...Copper fill ground on the component side Power fill on the circuit side of two layer boards Ground fill on both sides of four or more layer boards 4 1 2 Components From the following pins place components as close to the Fusion 878A as possible Connect a trace from the pin to the component on the component side when possible AGCCAP Pin 111 REFP Pin 112 VCCAP Pin 107 VRXP Pin 103 VCOMI Pin 104 VCOM...

Page 117: ...iety of combinations Measurements have been made and some increased noise reduction has been seen on some systems The noise improvements have not been substantial enough to warrant additional cost Additionally splitting planes requires close consideration to EMI and trace routing If split planes or regulators are desired some guidelines are included Digital terminating resistors should be connecte...

Page 118: ...on 878A follow these precautions Apply power to the device before or at the same time as you apply power to the interface circuit Connect all VDD VBB and VAA pins together through a low impedance plane Connect all BGND and AGND pins together through a low impedance plane If you are using a voltage regulator on the digital and or analog power planes use protection diodes See Figure 4 1 for an illus...

Page 119: ...ing on its location in the configuration space For a discussion on configuration cycle addressing refer to PCI Local Bus Specification Revision 2 2 The configuration space is accessible at all times even though it is not typically accessed during normal operation These registers are normally accessed by the Power On Self Test POST code and by the device driver during initialization time Software w...

Page 120: ...24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x4B 0x4C 0x50 31 16 0 Base Address 0 Register Max_Lat Min_Gnt Subsystem ID Subsystem Vendor ID AD 7 2 Device ID Device Control Vendor ID Revision ID Reserved Reserved Reserved Reserved Reserved Reserved VPD Capability Power Management Capability Power Management Support Registers VPD Data Reserved Reserved Reserved Latency Timer Header Type 0 Interrupt P...

Page 121: ...particular device or Part ID Code 15 0 RO 0x109E Vendor ID Identifies manufacturer of device assigned by the PCI SIG Bits Type Default Name Description 31 RR 0 Detected Parity Error Set when a parity error is detected in the address or data regardless of the Parity Error Response control bit 30 RR 0 Signaled System Error Set when SERR is asserted 29 RR 0 Received Master Abort Set when master trans...

Page 122: ...0 Class Code Fusion 878A is a multimedia video device 7 0 RO 0xXX Revision ID Current revision Bits Type Default Name Description 23 16 RO 0x80 Header type Multi function PCI device 15 8 RW 0x00 Latency Timer The number of PCI bus clocks for the latency timer used by the bus master Once the latency expires the master must initiate transaction termination as soon as GNT is removed Bits Type Default...

Page 123: ...terrupt Pin Fusion 878A interrupt pin is connected to INTA the only one usable by a single function device 7 0 RW Interrupt Line Communicates interrupt line routing information between the POST code and the device driver The POST code initializes this register with a value specifying to which input IRQ of the system interrupt controller the Fusion 878A interrupt pin is connected Device drivers can...

Page 124: ... assigned by SIG Bits Type Default Name Description 31 0 RW VPD Data Four bytes are always transferred between the VPD data register and the EEPROM The LSByte MSByte is transferred from to VPD_Adr VPD_Adr 3 Bits Type Default Name Description 31 27 RO 00000 PMC_PME PME cannot be asserted from this function 26 RO 0 PMC_D2 The function does not support the D2 power management state 25 RO 0 PMC_D1 The...

Page 125: ...ield indicates the scaling factor to be used when interpreting the value of the Pwr Data register Optional and not supported 12 9 RO 0000 Data_Select This field selects which data is to be reported through the Pwr Data register Optional and not supported 8 RO 0 PME_En Function does not support PME from D3cold 7 2 RO 000000 Reserved 1 0 RW 00 PowerState 1 This field determines the current power sta...

Page 126: ...ion of the byte enables Data to and from the video decoder scaler registers and VDFC comes from PCI byte lane 0 AD 7 0 only If the upper byte lanes are enabled for reading the data returned is 0 Thus each register is separated by a byte address offset of four All non used addresses are reserved locations and return an undefined value The scaling function needs to be controlled on a field basis to ...

Page 127: ...king some video sources will characteristically vary from line to line by more than one clock cycle so this bit will never be set 0 Device not in H lock 1 Device in H lock 5 RW 0 FIELD Field Status This bit reflects whether an odd or even field is being decoded 0 Odd field 1 Even field 4 RW 0 NUML This bit identifies the number of lines found in the video stream This bit is used to determine the t...

Page 128: ...X1 4 3 R0 11 Reserved 2 0 RW 000 FORMAT Automatic format detection may be enabled or disabled The NUML bit is used to determine the input format when automatic format detection is enabled 000 Auto format detect enabled 001 NTSC M input format 010 NTSC without pedestal Japan 011 PAL B D G H I input format 100 PAL M input format 101 PAL N input format 110 SECAM input format 111 PAL N combination inp...

Page 129: ...O_VACTIVE_LO Upon reset this register is initialized to 0xE0 VACTIVE_LO 0 is the LSB This 8 bit register is the lower byte of the 10 bit VACTIVE register The 2 MSBs of VACTIVE are contained in the CROP register VACTIVE defines the number of lines used in the vertical scaling process Bits Type Default Name Description 7 6 RW 00 VDELAY_MSB 1 The most significant two bits of vertical delay register 5...

Page 130: ...lower byte of the 10 bit HACTIVE register The two MSBs of HACTIVE are contained in the CROP register Horizontal Scaling Register Upper Byte 0x020 Even Field E_HSCALE_HI 0x0A0 Odd Field O_HSCALE_HI Upon reset this register is initialized to 0x02 This 8 bit register is the upper byte of the 16 bit HSCALE register Horizontal Scaling Register Lower Byte 0x024 Even Field E_HSCALE_LO 0x0A4 Odd Field O_H...

Page 131: ...ves the addition of a two s complement number to the luma channel Brightness can be adjusted in 255 steps from 128 to 127 The resolution of brightness change is 1 LSB 0 39 with respect to the full luma range Table 5 1 BRIGHT Parameters Hex Value Binary Value Brightness Changed By Numberof LSBs Percent of Full Scale 0x80 1000 0000 128 50 0x81 1000 0001 127 49 6 0xFF 1111 1111 01 0 39 0x00 1 0000 00...

Page 132: ...DC is disabled 0 Composite Video 1 Y C Component Video 5 RW 1 LDEC The luma decimation filter is used to reduce the high frequency component of the luma signal Useful when scaling to CIF resolutions or lower 0 Enable luma decimation using selectable H filter 1 Disable luma decimation 4 RW 0 CBSENSE This bit controls whether the first pixel of a line is a Cb pixel or a Cr pixel For example if CBSEN...

Page 133: ...s the LSByte of the luma gain contrast value Bits Type Default Name Description 7 0 RW 0xD8 CONTRAST_LO The CON_MSB bit and the CONTRAST_LO register concatenate to form the 9 bit CONTRAST register The value in this register is multiplied by the luminance value to provide contrast adjustment Table 5 2 CONTRAST Parameters Decimal Value Hex Value Percent of Original Signal 511 0x1FF 236 57 510 0x1FE ...

Page 134: ... the color difference paths must be the same i e the ratio between the value in the U gain register and the value in the V gain register should be kept constant at the default power up ratio When changing the saturation if the SAT_U_MSB bit is altered take care to ensure that the other bits in the CONTROL register are not affected Table 5 3 SAT_U_MSB SAT_U_LO Bits Type Default Name Description 7 0...

Page 135: ...both the color difference paths must be the same i e the ratio between the value in the U gain register and the value in the V gain register should be kept constant at the default power up ratio When changing the saturation if the SAT_V_MSB bit is altered take care to ensure that the other bits in the CONTROL register are not affected Table 5 4 SAT_V SAT_V_MSB SAT_V_LO Bits Type Default Name Descr...

Page 136: ...ddition of a two s complement number to the demodulating subcarrier phase Hue can be adjusted in 256 steps in the range 90 to 89 3 in increments of 0 7 NOTE S Not applicable to PAL SECAM or Digital Video Table 5 5 HUE Parameters Hex Value Binary Value Subcarrier Reference Changed By Resulting Hue Changed By 0x80 1000 0000 90 90 0x81 1000 0001 89 3 89 3 0xFF 1111 1111 0 7 0 7 0x00 0000 0000 1 00 00...

Page 137: ...ry is enabled 0 Low color detection and removal disabled 1 Low color detection and removal enabled 4 3 RW 00 HFILT These bits control the configuration of the optional 6 tap Horizontal Low Pass Filter The auto format mode determines the appropriate low pass filter based on the horizontal scaling ratio selected The LDEC bit in the CONTROL register must be programmed to 0 to use these filters 00 1 A...

Page 138: ...e region of the image are below a selected value The accumulated value determines the extent to which the AGC value needs to be raised in order to keep the SYNC level proportionate with the white level The UPCNT value is assumed positive for example 3F 63 3E 62 00 0 Bits Type Default Name Description 7 RW 0 RANGE Luma Output Range This bit determines the range for the luminance output on the Fusio...

Page 139: ...l scaling 6 RW 1 COMB Chroma Comb Enable This bit determines if the chroma comb is included in the data path If enabled a full line store is used to average adjacent lines of color information reducing cross color artifacts 0 Chroma comb disabled 1 Chroma comb enabled 5 RW 1 INT Used in conjunction with bit 7 FLDALIGN to align vertical scaling when overlaying fields at CIF resolution 60 50 Hz mode...

Page 140: ... the audio circuitry ARESET must be toggled at least once anytime the audio path is enabled 6 0 RW 000000 Reserved Must be set to zero for proper orientation Bits Type Default Name Description 7 0 RW 0x70 ADELAY AGC gate delay for back porch sampling Use the following equation to determine the value for this register ADELAY 6 8 µs 4 Fsc 15 Example for an NTSC input signal ADELAY 6 8 µs 14 32 MHz 1...

Page 141: ...sabled 3 RW 0 CLK_SLEEP When this bit is at a logical 1 the decoder clock is powered down but the device registers are still accessible Recovery time is approximately 1 s to return to capturing video 0 Normal clock operation 1 Shut down the system clock power down 2 RW 0 Y_SLEEP This bit enables putting the luma ADC in sleep mode 0 Normal Y ADC operation 1 Sleep Y ADC operation 1 RW 1 C_SLEEP This...

Page 142: ...the standard 64 clock wide HRESET 0 HRESET is 64 CLKx1 cycles wide 1 HRESET is 32 CLKx1 cycles wide 6 3 Reserved These bits should be written only with a logical 0 2 0 RW 000 VFILT These bits control the number of taps in the Vertical Scaling Filter Choose the number of taps in conjunction with the horizontal scale factor to ensure that the needed data does not overflow the internal FIFO 000 2 tap...

Page 143: ...ation 1 Enable vertical sync detection in determining the video presence PRES status 6 RW 1 WCFRAME This bit programs the rate at which the DNCNT and UPCNT values are accumulated 0 Once per field 1 Once per frame 5 0 RW 0x22F DNCNT The value programmed in these bits accumulates once per field or frame The accumulated value determines the extent to which the AGC value needs to be lowered in order t...

Page 144: ...enerator Address Reset 0 RW 00 0 Read write mode 1 Enable timing generator read mode NOTE S 1 The entire decoder will be running off the external clock GPCLK when GPCLK is activated Therefore the decoder functionality is subject to a halt condition if the input port is disconnected A clock detect circuit will allow the decoder to fall back on either the PLL or the XTAL whichever is enabled via PLL...

Page 145: ... normal 525 625 0x0B4 Total Line Count Register VTOTAL_HI Bits Type Default Name Description 7 0 RW 0x00 VTOTAL_LO The LSByte of the 10 bit VTOTAL register which sets the expected number of horizontal video lines to VTOTAL_LO number of horizontal video lines frame 1 Bits Type Default Name Description 7 2 RW 000000 Reserved 1 0 RW 00 VTOTAL_HI The 2 MSBs of the 10 bit VTOTAL register which sets the...

Page 146: ...4 2 2 0101 BtYUV 4 1 1 0110 Y8 Gray scale 0111 RGB8 Dithered 1000 YCrCb 4 2 2 Planar YUV12 1001 YCrCb 4 1 1 Planar YUV9 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Raw 8X Data 1111 Reserved 3 0 RW 0000 COLOR_EVEN Even Field Color Format 0000 RGB32 0001 RGB24 0010 RGB16 0011 RGB15 0100 YUY2 4 2 2 0101 BtYUV 4 1 1 0110 Y8 Gray scale 0111 RGB8 Dithered 1000 YCrCb 4 2 2 Planar 1001 YC...

Page 147: ... swapping of data entering the FIFO W2 31 16 is swapped with W0 15 0 2 RW 0 WSWAP_EVEN WordSwap Even Field A value of 1 enables word swapping of data entering the FIFO W2 31 16 is swapped with W0 15 0 1 RW 0 BSWAP_ODD ByteSwap Odd Field A value of 1 enables byte swapping of data entering the FIFO B3 31 24 is swapped with B2 23 16 and B1 15 8 is swapped with B0 7 0 0 RW 0 BSWAP_EVEN ByteSwap Even F...

Page 148: ...bit samples to capture while in VBI capture mode Bits Type Default Name Description 7 2 RW 000000 VBI_HDELAY The number of CLKx1 s to delay from the trailing edge of HRESET before starting VBI line capture 1 RW 0 EXT_FRAME A value of 1 extends the frame output capture region to include the 10 lines prior to the default VACTIVE region 0 RW 0 VBI_PKT_HI Upper bit for the number of raw data DWORDS fo...

Page 149: ...r 0 Use 6 for post divider 1 Use 4 for post divider 5 0 RW 000000 PLL_I PLL_I input 1 Range 6 63 If set to 0x00 then the PLL sleeps NOTE S 1 Minimum allowable PLL_I PLL_F 6 8000h 7 RW 0 Reserved 6 RW 0 VSIF_BCF Enables bypass of chroma filters Use when HSCALE is set to 0 1 Bypass chroma filters 0 Use chroma filters 5 RW 0 VSIF_ESO Enable Sync output for synchronizing video Input 1 Syncs are output...

Page 150: ...A controller detects a reserved unused opcode in the instruction sequence or reserved unused sync status in a SYNC instruction In general this includes any detected RISC instruction error 17 RR 0 PABORT Set whenever the initiator receives a MASTER or TARGET ABORT 16 RR 0 RIPERR Set when a data parity error is detected Parity Error Response must be set while the initiator is reading RISC instructio...

Page 151: ... begins a new video line or at the GPIO HRESET leading edge 1 RR 0 VSYNC Set when FIELD changes on the analog input or GPIO input 0 RR 0 FMTCHG Set when a video format change is detected i e the analog input changes from NTSC to PAL or vice versa Bits Type Default Name Description Bits Type Default Name Description 23 0 RW 0x000000 INT_MASK A value of 1 enables the interrupt bit The bits correspon...

Page 152: ...e output on GPCLK A value of 0 disables the output and enables GPCLK to supply the internal pixel clock during SPI 16 input mode otherwise this pin is assumed to be inactive 9 8 RW 00 Reserved This bit should only be written with a logical 0 7 6 RW 00 PLTP23 Planar mode trigger point for FIFO2 and FIFO3 00 4 DWORDs 01 8 DWORDs 10 16 DWORDs 11 32 DWORDs 5 4 RW 00 PLTP1 Planar mode trigger point for...

Page 153: ...or any future 1 byte transactions 1 Enables 1 byte read or write without START 3 RW 0 I2CSYNC I2 C synchronization 0 Disallows the slave to insert wait states 1 Allows the slave to insert bit level clock wait states 2 RW 0 I2CW3BRA Number of bytes sent and master slave acknowledge This bit has no meaning when I2CNOS1B bit 4 is high during a write transaction 0 Writes transaction of 2 bytes I2CDB 0...

Page 154: ...oller begins executing instructions at this address when RISC_ENABLE is set i e the RISC program counter is loaded with this pointer at the rising edge of RISC_ENABLE Bits Type Default Name Description 23 0 RW 0x000000 GPOE Writes to this register provide data to the output buffer enables A value of 1 enables the driver Bits Type Default Name Description 31 0 RO RISC_PC The current value of the RI...

Page 155: ...onfiguration space is accessible at all times even though it is not typically accessed during normal operation These registers are normally accessed by the Power On Self Test POST code and by the device driver during initialization time Software will however read the status register during normal operation when a PCI bus error occurs and is detected by Fusion 878A The configuration space is access...

Page 156: ...24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x4B 0x4C 0x50 31 16 0 Base Address 0 Register Max_Lat Min_Gnt Subsystem ID Subsystem Vendor ID AD 7 2 Device ID Vendor ID Revision ID Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Latency Timer Header Type 0 Interrupt Pin Interrupt Line Device Control 15 879A_049a Capabilities Pointer VPD Capability Power Management Cap...

Page 157: ...cular device or Part ID Code 15 0 RO 0x109E Vendor ID Identifies manufacturer of device assigned by the PCI SIG Bits Type Default Name Description 1 of 2 31 RR 0 Detected Parity Error Set when a parity error is detected in the address or data regardless of the Parity Error Response control bit 30 RR 0 Signaled System Error Set when SERR is asserted 29 RR 0 Received Master Abort Set when master tra...

Page 158: ...on 2 of 2 Bits Type Default Name Description 31 8 RO 0x048000 Class Code Fusion 878A is a multimedia other device 7 0 RO 0xXX Revision ID Current revision Bits Type Default Name Description 23 16 RO 0x80 Header Type Multi function PCI device Bits Type Default Name Description 15 8 RW 0x00 Latency Timer The number of PCI bus clocks for the latency timer used by the bus master Once the latency expir...

Page 159: ... 250 ns Affects the desired settings for the latency timer value This register is set to the max value even though the audio can tolerate up to 287 µs bus access latency a 0 setting would indicate no latency requirements 23 16 RO 0x04 Min_Gnt Requires a minimum grant burst period of 1 µs to empty data FIFO in units of 250 ns Affects the desired settings for the latency timer value Set for 32 DWORD...

Page 160: ...nctions 0 and 1 0 Disable 1 Enable NOTE S These control bits affect both Function 0 and Function 1 Bits Type Default Name Description 31 RW VPD_Flag This flag is set to a value of 1 when the device completes the reading and transfer of 4 bytes between the EEPROM and the VPD data register The flag is reset to 0 when the device completes a 4 byte write transaction SW initiates R or W transactions by...

Page 161: ...ot support the D2 power management state 25 RO 0 PMC_D1 This function does not support the D1 power management state 24 22 RO 000 Reserved 21 RO 1 PMC_DSI A value of 1 indicates that this function requires a device specific initialization sequence following transition to the D0 uninitialized state 20 RO 0 Reserved 19 RO 0 PMC_PME_Clk A value of 0 indicates that no PCI clock is required for the fun...

Page 162: ...ield indicates the scaling factor to be used when interpreting the value of the Pwr Data register Optional and not supported 12 9 RO 0000 Data_Select This field selects which data is to be reported through the Pwr Data register Optional and not supported 8 RO 0 PME_En Function does not support PME from D3cold 7 2 RO 000000 Reserved 1 0 RW 00 PowerState 1 This field determines the current power sta...

Page 163: ...he byte enable bits of the PCI bus The local memory mapped register address locations are specified as 12 bit offsets to the value loaded into the function s memory base address register The 8 bit byte address for each of the following register locations is AD 11 2 0x00 Any register may be written or read by any combination of the byte enables The following types specify how the Fusion 878A regist...

Page 164: ...uence or reserved unused sync status in a SYNC instruction In general this includes any detected RISC instruction error 17 RR 0 PABORT Set whenever the initiator receives a MASTER or TARGET ABORT 16 RR 0 RIPERR Set when a data parity error is detected Parity Error Response must be set while the initiator is reading RISC instructions RISC_ENABLE is reset by the target to stop the DMA immediately 15...

Page 165: ...ing request Bits Type Default Name Description 31 28 RW 0000 A_GAIN Audio input gain control offering 16 discrete linear steps from 0 5 to 3 0 See Table 2 12 Gain Control 27 RW 0 A_G2X Audio gain boost 0 Normal gain setting as specified in A_GAIN 0 5 Vrms standard input 1 Adds 6 dB input signal boost from pre amp 26 RW 0 A_PWRDN Analog audio power down 0 No power down 1 Power down the analog audio...

Page 166: ...80 and replacement with 0x8001 0x81 Mode determined by bit 14 DA_SBR 0 Disables 1 Enables 11 8 RW 0000 DA_SDR Specifies the DDF first stage and decimation rate Range 4 to 15 7 6 RW 00 DA_IOM Specifies audio digital audio I O mode 00 DA_IOM_AFE audio A D 01 DA_IOM_DA digital audio in 10 Reserved 11 Reserved 5 RW 0 DA_APP Enables Parallel Data mode DA_IOM 01 or High Speed Serial mode DA_IOM 00 0 Dis...

Page 167: ...n an audio line max value 4095 Bits Type Default Name Description 31 0 RW 0x00000000 RISC_IPC Base address for the RISC program Standard 32 bit memory space byte address although the software must DWORD align by setting the lowest 2 bits to 00 The DMA controller begins executing pixel instructions at this address when RISC_ENABLE is set For example the RISC program counter is loaded with this poin...

Page 168: ...6 0 Control Register Definitions Function 1 Fusion 878A 6 3 Local Registers Memory Mapped PCI Video Decoder 6 14 Conexant 100600B ...

Page 169: ...ditions Parameter Symbol Min Typ Max Units Power Supply Analog VAA VBB 4 75 5 00 5 25 V Power Supply Digital VDD 4 75 5 00 5 25 V Maximum VDD VAA 0 5 V MUX0 MUX1 MUX2 and MUX3 Input Range AC coupling required 0 5 1 00 2 00 V CIN Amplitude Range AC coupling required 0 5 1 00 2 00 V STV SFM SML Input Range AC coupling required 0 5 1 00 VRMS Ambient Operating Temperature TA 0 70 C ...

Page 170: ...on is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 2 This device employs high impedance CMOS devices on all signal pins It must be handled as an ESD sensitive device Voltage on any signal pin that exceeds the power supply voltage by more than 0 5 V or drops below ground by more than 0 5 V can induce destructive latchup Table 7 3 DC C...

Page 171: ...V CIN 5 pF Digital Outputs PCI Outputs Output High Voltage IOH 2 mA VOH 2 4 VDD V Output Low Voltage IOL 6 mA VOL 0 55 V GPIO Output High Voltage IOH 1 2 mA VOH 2 4 VDD V Output Low Voltage IOL 6 mA VOL 0 4 V 3 State Current IOZ 10 µA Output Capacitance CO 5 pF I2 C Output Output Low Voltage IOL 3 mA VOL 0 4 V Analog Pin Input Capacitance CA 5 pF Table 7 3 DC Characteristics 2 of 2 Parameter Symbo...

Page 172: ...ired FS 28 63493 28 63636 28 63779 MHz XTI Input Cycle Time High Time Low Time 1 2 3 14 14 34 92 ns ns ns Figure 7 1 Clock Timing Diagram XTI 1 2 3 879A_050 Table 7 5 Power Supply Current Parameters Parameter Symbol Min Typ Max Units Supply Current VAA VDD 5 0 V FS2 28 64 MHz T 25 C VAA VDD 5 25 V FS2 35 47 MHz T 70 C VAA VDD 5 25 V FS2 35 47 MHz T 0 C Supply Current Power Down 240 75 320 330 mA m...

Page 173: ...Units Horizontal Lock Range 7 of Line Length Fsc Lock in Range 800 Hz Gain Range 6 6 dB NOTE S Test conditions unless otherwise specified Recommended Operating Conditions TTL input values are 0 V to 3 V with input rise fall times 3 ns measured between the 10 and 90 points Timing reference points at 50 for digital inputs and outputs Pixel and control data loads 30 pF and 10 pF GPCLK load 50 pF See ...

Page 174: ...des a mechanical drawing of the 128 pin PQFP package Figure 7 3 128 pin PQFP Package Mechanical Drawing ALL DIMENSIONS IN MILLIMETERS S Y M B O L MIN NOM MAX A A1 A2 D D1 E E1 L e b 0 25 2 57 0 65 0 13 3 04 0 33 2 71 23 20 BSC 20 00 BSC 17 20 BSC 14 00 BSC 0 70 0 50 BSC 3 40 2 87 0 95 0 25 TOP VIEW BOTTOM VIEW D1 E E1 D b e A A2 A1 1 60 063 REF L 879A_053 ...

Page 175: ...ut Output System BSDL Boundary Scan Descriptive Language BTSC MTS Broadcast Television Systems Committee Multichannel Television Sound CCIR 601 A Recommendation From The International Radio Communications Committee CIF Common Interchange CMOS Complementary Metal Oxide Semiconductor CPU Central Processing Unit DAP Digital Audio Packetizer DDF Digital Decimation Filter DMA Direct Memory Access DWORD...

Page 176: ...essing Unit MSB Most Significant Bit MSByte Most Significant Byte MUX Multiplexer multiplex NTSC National Television Standards Committee an American video standard Opcode Operational Code PAL A European video standard PCB Printed Circuit Board PCI Peripheral Component Interconnect PLL Phase Lock Loop POST Power on Self Test PQFP Plastic Quad Flat Pack QCIF Quarter RC Resister Capacitor RGB Red Gre...

Page 177: ...ix A Acronym List PCI Video Decoder 100600B Conexant A 3 VCR Video Cassette Recorder VDFC Video Data Format Conversion VFE Video Front End VPD Vital Product Data VTC Video Timing Controller Y C Luminance And Chrominance ...

Page 178: ...Appendix A Acronym List Fusion 878A PCI Video Decoder A 4 Conexant 100600B ...

Page 179: ......

Page 180: ...Fax 61 2 9869 4077 China Phone 86 2 6361 2515 Fax 86 2 6361 2516 Hong Kong Phone 852 2827 0181 Fax 852 2827 6488 India Phone 91 11 692 4780 Fax 91 11 692 4712 Korea Phone 82 2 565 2880 Fax 82 2 565 1440 Phone 82 53 745 2880 Fax 82 53 745 1440 Europe Headquarters Conexant Systems France Les Taissounieres B1 1681 Route des Dolines BP 283 06905 Sophia Antipolis Cedex FRANCE Phone 33 4 93 00 33 35 Fax...

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