RCIM User’s Guide
A-8
Figure A-4 RCIM IV Interrupt Enable/Request/Pending/Clear/Arm/Level/Polarity Registers
The enable registers enable the selected interrupts.
The request registers are software driven requests of the selected interrupts.
The pending registers are pending requests.
The clear registers clear the selected interrupts.
The arm registers arm the selected interrupts for edge triggering.
The level registers set level (1) or edge (0) for the selected interrupts.
The polarity registers set polarity high (1) or low (0) for the selected interrupts.
Offsets: 00010, 00014, 00020, 00024, 00030, 00034, 00040, 00044, 00050, 00054, 00060, 00064
Register #1
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CI
AUX
Reserved
EI
RTC
7
6
5
4
3
2
1
0
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CI
=
Cable Interrupt
AUX =
Auxiliary Interrupt
EI
=
External Interrupt
RTC =
RTC Interrupt
Register #2
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
CI
Reserved
EI
Reserved
11 10 9
8
11 10 9
8
AUX 2 = GPS RX Buffer Full
AUX 1 = GPS TX Buffer Empty
AUX 3 = IRIG Pulse Per Second
AUX 0 = GPS Pulse Per Second
Summary of Contents for RCIM
Page 1: ...Real Time Clock and Interrupt Module RCIM User s Guide 0898007 1000 March 2021...
Page 10: ...RCIM User s Guide 1 4...
Page 32: ...RCIM User s Guide 2 22...
Page 80: ...RCIM User s Guide A 28...
Page 102: ...RCIM User s Guide C 2...
