9.6
Interrupt Control Register
This register is at I/O address 215h. It provides control over interrupts from the IPMI.
7
6
5
4
3
2
1
0
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RFU
GPI
SMS_ATN
SMIC
RFU
GPI
SMS_ATN
SMIC
INT FLAG INT FLAG NOT BUSY
INT ENA
INT ENA
NOT BUSY
INT FLAG
INT ENA
Bit 0: SMIC Not Busy Interrupt Enable (Read/Write)
This bit allows an interrupt to be generated when the P89C664 microcontroller clears the SMIC
BUSY flag.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: SMS_ATN Interrupt Enable (Read/Write)
This bit allows an interrupt to be generated when the P89C664 microcontroller sets the SMIC
SMS_ATN bit.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: General Purpose Interrupt (GPI) Interrupt Enable (Read/Write)
This bit allows an interrupt to be generated when the P89C664 microcontroller sets the GPI INT
FLAG bit.
0 = GPI not enabled
1 = GPI enabled
Bit 3: Reserved
Bit 4: SMIC Not Busy Interrupt Flag (Read/Clear)
0 = event has not occurred
1 = event has occurred
Writing zero to this bit will clear it to zero, writing one will leave it as is.
Bit 5: SMS_ATN Interrupt Flag (Read/Clear)
0 = event has not occurred
1 = event has occurred
Writing zero to this bit will clear it to zero, writing one will leave it as is.
Bit 6: General Purpose Interrupt (GPI) Interrupt Flag (Read/Clear)
The IPMI microcontroller sets this bit to request an interrupt. If the GPI Interrupt Enable bit is also
set, an interrupt (INT 5) will be generated. Note that if the interrupt is not required, the
microcontroller can use this bit to signal status to the processor.
0 = no interrupt request
1 = interrupt request
Writing zero to this bit will clear it to zero, writing one will leave it as is.
Bit 7: Reserved
9-8
PP 110/01x
Additional Local I/O Functions
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