SLM-3650 Satellite Modem
Revision 3
Options
MN/SLM3650.IOM
A–58
BUF
PLL
SAT
INT
RXD
MC
EXT
TERR
TT
RT
DDS
EXT
REF
INT
RXD
RXC
Note:
PLL will be bypassed when the RX data rate is set to the TX data rate. This will disable
the Asymmetrical Mode.
Figure A-13. Receive Section of the Asymmetrical Loop Timing Block Diagram
Example:
Master/Slave Clocking Setup:
1. Master site has a 10 MHz clock that is needed as the clock source.
2. Unequal data rates: 4.096 Mbps and 2.152 Mbps (numbers divisible by 8).
Master Site Option No. 1:
1. Set Configuration/Modulator/Modem Reference to EXT 10 MHz.
2. Set Configuration/Interface/TX Clock Source to SCT (Internal).
Note:
The SCT clock is slaved off of the 10 MHz input. The 10 MHz reference
should be placed into CP3 of the modem.
3. Set Configuration/Interface/Buffer Clock to SCT (Internal).
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
