REG26(2)
Alternating I/Q
bits
Alternating bits are sent on the I and Q
channels. The symbol rate must be identical
on both I and Q channels. Two independent
FEC decoders are used on the I and Q paths
respectively.
Enabled(1)/Disabled(0)
REG26(7)
½ symbol delay
on the Q path
The Q bits received with a ½ symbol delay
with respect to the I bits.
Enabled(1)/Disabled(0)
REG26(6)
Encoding
0 = NRZ-L
1 = NRZ-M
2 = NRZ-S
4 = Biphase-L
REG26(5:3)
AGC response
time
Users can to optimize AGC response time
while avoiding instabilities (depends on
external factors such as gain signal filtering
at the RF front-end and chip rate). The
AGC_DAC
gain control signal is updated as
follows
0 = every chip,
1 = every 2 input chips,
2 = every 4 input chips,
3 = every 8 input chips, etc….
10 = every 1000 input chips.
Valid range 0 to 14.
REG28(4:0)
Viterbi decoding Disable (0) / Enable (1)
REG27(1)
Viterbi decoder
G2 parity bit
inversion
No (0) / Yes (1)
REG27(2)
Select BER
tester input
0 = I,
1 = Q
REG27(3)
Built-in DSSS modulator (when instantiated)
Parameters
Configuration
DSSS modulator
enable
0 = disabled
1 = enabled
REG61(7)
Channel 1
modulator input
selection
0 = disabled
1 = TCP server at port 1280
2 = PRBS11 test sequence
3 = zeros
REG63(5:4)
Channel 2
modulator input
selection
0 = disabled
1 = TCP server at port 1281
2 = PRBS11 test sequence
3 = zeros
REG65(5:4)
I Code
Linear feedback shift register
initialization.
As per [1]
REG62 LSB
REG63(2:0) MSb
Q Code
REG64 LSB
REG65(2:0) MSb
Code mode
0 = forward command link (see SNIP)
1 = return mode 2 link
See SNIP for details
REG65(3)
Chip rate
(
fchip rate
)
The nominal chip rate is 3.077799479166
Mchips/s. However, the design is
somewhat more flexible. Alternative chip
rates can be entered here
32-bit integer expressed as
fchip rate
* 2
32
/
f
clk_p
.
The maximum practical chip rate is
f
clk_p
/
2.
Nominal chip rate: 0x064DA730
REG66 (LSB) – REG69 (MSB)
I channel
symbol rate
f
symbol_rate
The I-channel symbol rate can be set
independently of the spreading code
period as
f
symbol_rate
* 2
32
/
f
clk_p
Example: 0x0346DC5 represents 100
Ksymbols/s.
REG70 (LSB) – REG73 (MSB)
Q channel symbol
rate
f
symbol_rate
The Q-channel symbol rate can be set
independently of the spreading code
period as
f
symbol_rate
* 2
32
/
f
clk_p
REG74(LSB) – REG77 (MSB)
8