Control Registers
The module configuration parameters are stored in
volatile (SRT command) or non-volatile memory
(SRG command). All control registers are
read/write.
Several key parameters are computed on the basis
of the 125 MHz internal processing clock
f
clk_p
:
frequency translation, chip rate, etc.
Built-in DSSS demodulator
Parameters
Configuration
SDDS-
formatted
stream input
selection
1 = UDP port 29495
0 = TCP port 1028
REG0(0)
Demod input
selection
0 = SDDS / LAN
2 = A/D converters baseband
3 = A/D converters IF undersampling
4 = internal modulator loopback
REG28(7:5)
I Code
Linear feedback shift register initialization.
As per [1]
REG1 LSB
REG2(2:0) MSb
Q Code
REG3 LSB
REG4(2:0) MSb
Code mode
0 = forward command link
1 = return mode 2 link
See SNIP for details
REG27(4)
reserved
REG27(7:5) = “000”
CIC_R
Decimation ratio.
Largest integer less than
input sampling rate / 4*chip rate
REG2(7:3): lsbs
REG4(7:3): msbs
Chip rate
(
fchip rate
)
The nominal chip rate is 3.077799479166
Mchips/s. However, the design is somewhat
more flexible. Alternative chip rates can be
entered here
32-bit integer expressed as
fchip rate
* 2
32
/
f
clk_p
.
The maximum practical chip rate is
f
clk_p
/2.
Nominal chip rate: 0x064DA741
The maximum allowed error between
transmitted and received chip rate is +/-
100ppm.
REG5 (LSB) – REG8 (MSB)
I channel symbol
rate
f
symbol_rate
The I-channel symbol rate can be set
independently of the spreading code period
as
f
symbol_rate
* 2
32
/
f
clk_p
Example: “00346DC6” represents 100
Ksymbols/s.
REG9 (LSB) – REG12 (MSB)
Q channel
symbol rate
f
symbol_rate
The Q-channel symbol rate can be set
independently of the spreading code period
as
f
symbol_rate
* 2
32
/
f
clk_p
REG13 (LSB) – REG16 (MSB)
I channel
spreading
factor
(Processing
gain)
Approximate (i.e rounded) ratio of chip
rate / symbol rate
REG17 (LSB)
REG18(4:0) MSb
Q channel
spreading
factor
(Processing
gain)
Approximate (i.e rounded) ratio of chip
rate / symbol rate
REG19 (LSB)
REG20(4:0) MSb
Nominal input
center
frequency (
f
c
)
The nominal center frequency is a fixed
frequency offset applied to the SDDS input
samples. It is used for fine frequency
corrections, for example to correct clock
drifts.
32-bit signed integer (2’s complement
representation) expressed as
f
c
* 2
32
/
f
clk_p
In addition to this fixed value, an optional
time-dependent frequency profile can be
entered.
REG21 (LSB) – REG24 (MSB)
Reserved
REG25
Spectrum
inversion
Invert Q bit
0 = off
1 = on
REG26(0)
BPSK / SQPN
0 = BPSK
1 = SQPN
REG26(1)
SQPN
single/double
source
0 = different data on I and Q channels
(including the case when bits of a single
input bit stream are sent alternatively to the
I/Q channels). Independent symbol rates on
I/Q channels. Uses two FEC decoders.
1 = identical data on I and Q channels (prior
to coherent sum). Uses one FEC decoder.
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