The input sampling rate is read from the SDDS
preamble. The receiver design was verified at an
input sampling rate of 6.25 MSamples/s, but the
design should work similarly at other sampling
rates.
The 64-bit receiver time is read from each SDDS
frame preamble. It is used to time-tag the output
frames containing the demodulated bits.
External frequency reference
A 10 MHz external frequency reference is required
for proper operation. The electrical characteristics
are as follows:
Sinewave, clipped sinewave or squarewave. AC-
coupled.
Minimum level: 2Vpp.
Maximum level: 5Vpp.
When the SDDS input stream is transmitted as
UDP, it is essential that the same 10 MHz be used
at both ends of the UDP link, otherwise buffer
underflow or overflow conditions may occur.
When the SDDS input stream is transmitted as
TCP, the 10 MHz frequency stability requirements
are not as stringent as the TCP protocol informs the
data source of flow-control conditions at the data
sink. In this case, the data source is responsible for
timing adjustments in the data throughput.
Modulator input stream
The modulator has two independent external inputs
for the I and Q channels. Inputs are through the
LAN xA connectors on the back panel.
Two TCP servers await connections from remote
TCP clients on ports 1280 and 1281 for the I and Q
channels respectively.
The TCP clients must send input data as fast as
allowed by the TCP flow control in order to prevent
an underflow condition at the modulator.
Spreading codes
The demodulator is designed to acquire two types
of Gold codes:
-
All forward command link codes (1023-
chip Gold codes)
-
All return mode 2 link codes (2047-chip
Gold codes)
The Gold codes selection is performed by
entering 10 or 11-bit initialization vectors for
the linear feedback shift registers. Appendix A
of document 451-PN CODE-SNIP lists these
initialization vectors as ‘I-code’ and ‘Q-code”.
For example, NASA return mode 2 link code 40 is
selected by entering 2225o (octal) and 1337o in the
appropriate control registers.
Symbol Rate
The demodulation symbol rates on the I and Q
channels are independent of the chip rate and code
period. The demodulator includes two autonomous
symbol tracking loops, separate from the code
tracking loop.
However, the full spread-spectrum processing gain
can only be achieved if the symbol period is less
than the 2047-chip code period.
Frequency Tracking
The DSSS demodulator is capable of acquiring
signals with a maximum center frequency error of
+/- 5 KHz remaining after fixed and dynamic
(frequency profile table) compensation.
Two features assist the demodulator in extending
this natural frequency acquisition range:
1. a fixed user-defined frequency offset,
entered through the GUI, is applied to the
received signal.
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