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ComBlock COM-1826, Manual, Page: 6 / 18

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ComBlock COM-1826 Manual Download Page 6

Configuration (Advanced)

Alternatively, users can access the full set of  configuration features by specifying 8-bit control registers as 
listed below. These control registers can be set manually through the ComBlock Control Center or by software 
using the ComBlock API (see 

www.comblock.com/download/M&C_reference.pdf

) 

All control registers are read/write. Definitions for the 

Control registers

 and 

Status registers

 are provided below.

6

Summary of Contents for COM-1826

Page 1: ...es Demodulation performances within 1 5 dB from theory at threshold Eb No of 2 dB Demodulated bits encapsulated in UDP frames and sent out to the LAN Support for IGMPv2 multicast addressing Monitoring o Receiver lock Carrier frequency error SNR ComScope enabled key internal signals can be captured in real time and displayed on host computer 90VAC 264VAC power supply Options o 1 3 receivers per 1 R...

Page 2: ... coherent I D Re sampling Digital frequency translation Noise power x NACQ parallel detection circuits Code tracking loop Skip 1 2 chips False code lock detection Code acquisition State machine Carrier lock early center late bins 3 baseband complex samples Despreading with on time code replica to PSK demodulator I D Symbol timing NCO to PSK demodulator Symbol timing loop PSK demodulator DSSS demod...

Page 3: ...ule configuration is stored in non volatile memory Configuration Basic The easiest way to configure the COM 1826 is to use the ComBlock Control Center software supplied with the module on CD In the ComBlock Control Center window detect the ComBlock module s by clicking the Detect button next click to highlight the COM 1826 module to be configured next click the Settings button to display the Setti...

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Page 6: ...ontrol registers as listed below These control registers can be set manually through the ComBlock Control Center or by software using the ComBlock API see www comblock com download M C_reference pdf All control registers are read write Definitions for the Control registers and Status registers are provided below 6 ...

Page 7: ...LSB REG8 MSB I channel symbol rate fsymbol_rate The I channel symbol rate can be set independently of the spreading code period as fsymbol_rate 232 fclk_p Example 00346DC6 represents 100 Ksymbols s REG9 LSB REG12 MSB Q channel symbol rate fsymbol_rate The Q channel symbol rate can be set independently of the spreading code period as fsymbol_rate 232 fclk_p REG13 LSB REG16 MSB I channel spreading f...

Page 8: ...meters Configuration DSSS modulator enable 0 disabled 1 enabled REG61 7 Channel 1 modulator input selection 0 disabled 1 TCP server at port 1280 2 PRBS11 test sequence 3 zeros REG63 5 4 Channel 2 modulator input selection 0 disabled 1 TCP server at port 1281 2 PRBS11 test sequence 3 zeros REG65 5 4 I Code Linear feedback shift register initialization As per 1 REG62 LSB REG63 2 0 MSb Q Code REG64 L...

Page 9: ... Gaussian noise Because of the potential for saturation please check for saturation when changing this parameter Saturation can easily be checked by visualizing the input signal using ComScope REG31 LSB REG32 MSB External transmitter gain control When using an external transceiver such as the COM 350x family the transmitter gain can be controlled through the TX_GAIN_CNTRL1 analog output signal Ran...

Page 10: ...ck PLL lock Indirectly confirms the presence of the frequency reference TCXO for firmware option A external 10 MHz for firmware option B 1 locked 0 unlocked SREG9 1 Input sampling rate The sampling rate as read from the SDDS input stream Format sampling_rate fclk 2 32 SREG10 bit 7 0 LSB SREG11 bit 15 8 SREG12 bit 23 16 SREG13 3 0 bit 27 24 MSB Time tag Last valid timetag read from the SDDS input h...

Page 11: ...pute the signal to noise ratio after despreading as S N The absolute value is meaningless because of multiple agcs SREG53 LSB SREG54 MSB Noise power N Average noise power Used to compute the SNR after despreading The absolute value is meaningless because of multiple agcs SREG55 LSB SREG56 MSB SNR 2 S N N ratio valid only during code lock Linear not in dBs Fixed point format 14 2 SREG57 LSB SREG58 ...

Page 12: ...t signed 1 sample symbol 512 4 Averaged signal power valid only during code tracking 8 bit signed fclk 512 Trace 3 signals Format Nominal sampling rate Buffer length samples 1 Code tracking phase correction accumulated 8 bit signed 2 samples symbol 512 2 Carrier fine tracking phase 8 bit signed fclk 512 3 I Symbol tracking phase accumulated 8 bit signed 1 sample symbol 512 4 Averaged noise power v...

Page 13: ...lses every 2047 bits when receiving a PRBS 11 test sequence Operation Monitoring Control M C is possible over USB and LAN TCP A pre requisite for using USB is the prior installation of the ComBlock USB driver Monitoring and control is through the USB and LAN xA connectors on the back panel At manufacturing the default M C LAN address is 172 16 1 2 It can be subsequently changed via USB or LAN TCP ...

Page 14: ... on ports 1280 and 1281 for the I and Q channels respectively The TCP clients must send input data as fast as allowed by the TCP flow control in order to prevent an underflow condition at the modulator Spreading codes The demodulator is designed to acquire two types of Gold codes All forward command link codes 1023 chip Gold codes All return mode 2 link codes 2047 chip Gold codes The Gold codes se...

Page 15: ...nd starting at the specified SDDS start time The receiver interpolates linearly 64x between successive 1s samples so as to minimize discontinuities This ensures phase and frequency continuity This frequency bias is removed from the SDDS input samples for the playback duration irrespective of the demodulator lock status Table playback is mutually exclusive with table upload Opening a new TCP sessio...

Page 16: ...tes are transmitted no partially filled bytes Modulator The built in modulator includes the FEC encoding and DSSS baseband modulation functions The modulator output can be directed to the internal demodulator when the loopback control is enabled Depending on the ordering option the modulator output can also be directed to analog baseband or RF Load Software Updates From time to time ComBlock softw...

Page 17: ...ly if the IP address is known defined for the personality index selected as default Once this is done the user can safely re load a valid FPGA configuration file into flash memory using the ComBlock Control Center UDP Reset Port 1029 is open as a UDP receive only port This port serves a single purpose being able to reset the modem and therefore the TCP IP connection gracefully This feature is inte...

Page 18: ... may have occurred in the RF transmission chain If so invert the spectrum inversion flag at the demodulator Configuration Management This specification is to be used in conjunction with VHDL software revision 0 and ComBlock control center revision 3 10g and above It is possible to read back the option and version of the FPGA configuration currently active Using the ComBlock Control Center highligh...

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