Schematic Diagrams
Processor 7/7 B - 9
B.Sch
e
m
a
tic D
iag
rams
Processor 7/7
VREF_CH_A_DIMM
Q12
*AO3402L
G
D
S
R203
1K_1%_04
R202
1K_1%_04
Q11
*AO3402L
G
D
S
R212
1K_1%_04
R210
1K_1%_04
DRAMRST_CNTRL 3,15
1.5V
1.5V
MVREF_DQ_DIMMA 9
DRAMRST_CNTRL
DRAMRST_CNTRL
MVREF_DQ_DIMMB 10
VREF_CH_B_DIMM
R46
*1K_04
RE
SE
RV
E
D
U23E
47989-0732
CFG[0]
AK28
CFG[1]
AK29
CFG[2]
AL26
CFG[3]
AL27
CFG[4]
AK26
CFG[5]
AL29
CFG[6]
AL30
CFG[7]
AM31
CFG[8]
AM32
CFG[9]
AM30
CFG[10]
AM28
CFG[11]
AM26
CFG[12]
AN28
CFG[13]
AN31
CFG[14]
AN26
CFG[15]
AM27
CFG[16]
AK31
CFG[17]
AN29
RSVD34
AM33
RSVD35
AJ27
RSVD38
J16
RSVD42
AT34
RSVD39
H16
RSVD40
G16
RSVD41
AR35
RSVD43
AT33
RSVD45
AR34
RSVD56
AT2
RSVD57
AT1
RSVD58
AR1
RSVD46
B34
RSVD47
A33
RSVD48
A34
RSVD49
B35
RSVD50
C35
RSVD51
AJ32
RSVD52
AK32
RSVD30
AE7
RSVD31
AK2
RSVD28
L7
RSVD29
AG7
RSVD27
J15
RSVD16
C30
RSVD15
D23
RSVD17
A31
RSVD18
B30
RSVD20
D30
RSVD19
B29
RSVD22
A30
RSVD21
B31
RSVD23
C29
RSVD24
J20
RSVD37
T8
RSVD6
B4
RSVD7
D1
RSVD8
F25
RSVD9
F24
RSVD11
D24
RSVD12
G25
RSVD13
G24
RSVD14
E23
RSVD32
W8
RSVD33
AT26
RSVD25
B18
RSVD44
AP35
RSVD10
F23
RSVD5
AJ26
VAXG_VAL_SENSE
AJ31
VSSAXG_VAL_SENSE
AH31
VCC_VAL_SENSE
AJ33
VSS_VAL_SENSE
AH33
KEY
B1
VCC_DIE_SENSE
AH27
VCCIO_SEL
A19
RSVD54
AN35
RSVD55
AM35
CFG6
CFG5
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG[6:5]
PCIE Port Bifurcation Straps
R40
*1K_04
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG7
CFG7
3.3V
2,3,11,14,15,18,23,24,26,28,29,30,32,33,36,37,39,40
R214
*1K_04
CFG2
CFG2
CFG4
CFG Straps for Processor
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4
H_CPU_RSVD1
H_CPU_RSVD4
H_CPU_RSVD3
H_CPU_RSVD2
CFG7
CFG4
CFG2
CFG6
CFG0
CFG5
R31
*1K_04
R213
*0_04
R209
*1K_04
1.5V
3,6,9,10,21,26,28,29,36,37
R206
*0_04
R45
*1K_04
R41
*1K_04
Sandy Bridge Processor 7/7
( RESERVED )
VREF_CH_A_DIMM
VREF_CH_B_DIMM
R381
*10mil_04
3.3V
R380
10K_04
H_SNB_IVB#_PWRCTRL
Sheet 8 of 48
Processor 7/7
Summary of Contents for W130HU
Page 1: ...W130HU W130HV ...
Page 2: ......
Page 3: ...Preface I Preface Notebook Computer W130HU W130HV Service Manual ...
Page 12: ...Preface X Preface ...
Page 26: ...Introduction 1 12 1 Introduction ...
Page 42: ...Disassembly 2 16 2 Disassembly ...
Page 45: ...Top A 3 A Part Lists Top Figure A 1 Top ...
Page 46: ...A 4 Bottom A Part Lists Bottom Figure A 2 Bottom 長騰 ...
Page 47: ...HDD A 5 A Part Lists HDD Figure A 3 HDD ...
Page 48: ...A 6 LCD A Part Lists LCD Figure A 4 LCD ...
Page 98: ...Schematic Diagrams B 50 B Schematic Diagrams ...