CJB CJ ISA-E5, User Manual, Page: 62 / 90

54 ISA-E5 User`s Manual
DRAM Clock/Drive Control
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Clock/Drive Control
Current FSB Frequency 100MHz
Current DRAM Frequency 200MHz
DRAM Clock [By SPD]
DRAM Timing [Auto By SPD]
X SDRAM CAS Latency [DDR/DDR 2.5/ 4
X Bank Interleave Disabled
X Precharge to Active (Trp) 2T
X Active to Precharge (Tras) 05T
X Active to CMD (Trcd) 4T
X REF to ACT/REF (Trfc) 21T
X ACT (0) to ACT (1) (TRRD) 3T
Item Help
Menu Level
↑↓→←
: Move Enter: /-/PU/PD: Value F10: Save ESC: Exit F1:General Help
F5: Previous Values F6: Fail-safe Defaults F7: Optimized Defaults
Current FSB Frequency
The choice: 100MHz.
Current DRAM Frequency
The choice: 200MHz.
DRAM Clock
The choice: By SPD, 100MHz, 133MHz, 166MHz, 200MHz.
DRAM Timing
The choice: Manual, Auto By SPD.
SDRAM CAS Latency [DDR/DDR2]
The choice: 1.5/ 2, 2/ 3, 2.5/ 4, 3/ 5.
Bank Interleave
The choice: Disabled, 2 Bank, 4 Bank, 8 Bank.