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4.16 PSEUDO-SRAM CONNECTING METHOD
In the system consisted of the CPU and gate array, S-RAM may be used as the work area as the print data buffer, bit
data development, etc.. This gate array supports Self-Refresh so that a pseudo-SRAM can be easily connected.
Use the PS-RAM which integrates OE and RFSH pins into one.
4.17 OTHER CONTROL TERMINALS
As for functions of control pins of this gate array, refer to the
following table:
SIGNAL NAME PIN NO FUNCTION
RES
94
Connects system reset. When being set to low level, this is reset.
RESO
95
Connects watchdog timer output. When being set to low level, this is reset.When in high
level, reset is canceled with rising of CS0.
CS0
96
Connects Chip Select signal of the watchdog timer. To output from CPU, connect Chip
Select signal of System ROM.
CS1
97
Chip Select When set to low level, transfers and controls data between the gate array and
CPU.
HWR
98
Write Control When set to low level, data are written through data bus.
RD
99
Read Control When set to low level, data are read through data bus.
