11
4.6
INTERNAL ADDRESS MAP
A3
A2
A1
A0
RD
HWR
CS1 OPERATION AND APPLICABLE PORT
0
0
0
0
0
1
0
Prohibited
0
0
0
0
1
0
0
Print data buffer
0
0
0
1
0
1
0
Prohibited
0
0
0
1
1
0
0
DMA request
0
0
1
0
0
1
0
PAI port input
0
0
1
0
1
0
0
PA0 port output & address latch output
0
0
1
1
0
1
0
PBI port input
0
0
1
1
1
0
0
Prohibited
0
1
0
0
0
1
0
PCI port input & Centro-data input
0
1
0
0
1
0
0
PC0 port output (PBUSY)
0
1
0
1
0
1
0
180° turning output
0
1
0
1
1
0
0
Bit data buffer for processing
0
1
1
0
0
1
0
Double width lower 8-bit output
0
1
1
0
1
0
0
0
1
1
1
0
1
0
Double width upper 8-bit output
0
1
1
1
1
0
0
Head control mode register
1
X
X
X
0
1
0
90 °turning output
1
X
X
X
1
0
0
90 °turning data buffer
X
X
X
X
X
X
1
Data bus high impedance
X
X
X
X
1
1
0
Data bus high impedance
X mark indicates either "0" or "1".
Ports other than those listed above are subject to independent operation.
