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14
The whole sequence is shown as follows:
4.8
RESET CIRCUIT
With RES pin (No 94 pin) set to "Low" level, STB 1
㨪
3 (No's 9
㨪
11 pins) are made in high impedance state cutting
off current supply to Thermal Head. Perform pull-up or pull-down according to Thermal Head. Further, with a
watchdog timer output (CPU, etc.) connected to RESO pin (No 95 pin), checking is performed on every ROM access
time, thus protecting Thermal Head.
For other output pins, those with pull-up are made "High", while those without are made high impedance. Refer to
the above mentioned "Terminals and Their Functions."
Recommended Reset IC: SEIKO Electronic Co., Ltd. S-804HNM
The gate array, when Reset pin (Pin 94) is held at "low" level for 1
P
s or more and returned to "high" level under
supply voltage of 5V
r
5%, is reset released and initialized.