Configuring Cisco Multimode G.SHDSL EFM/ATM in Cisco ISR G2
Configuring Cisco G.SHDSL EFM/ATM
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Configuring Cisco Multimode G.SHDSL EFM/ATM in Cisco ISR G2
IRQ2 Int 0 IRQ1 Int 0
Int Frame Network Int 0x01
Error Interrupt Event (0xA94B6BF):
GDF Rx Resume Error Event 1
Rx Done Error Event 0 Card Present Change Event 0
Hwic Int Frame Error Event 0x0B Tx First Last Error Event 0
Tx Done Error Event 1 IRQ2 Event 1
IRQ1 Event 0 Host Specific Error Event 1
Rx Overrun Event 0 DDR RxClk Missing Event 1
Reg RW Timeout Event 1 Reg RW Error Event 1
Rx CRC Event 1 Rx Format Error Event 1
DMA Error Event 1
Management Interrupt Event (0x9072):
Hwic Int Frame Mgmt Event 0x09
IRQ2 Int 0
IRQ1 Int 0 Graceful Stop Tx Event 0
Network Interrupt Event (0x24222044):
GDF Ring 3 Interrupt Events:
Rx Frame Drop Event 0 Generic Frame Tx Event 0
Generic Frame Rx Event 0
GDF Ring 2 Interrupt Events:
Rx Frame Drop Event 1 Generic Frame Tx Event 0
Generic Frame Rx Event 0
GDF Ring 1 Interrupt Events:
Rx Frame Drop Event 0 Generic Frame Tx Event 1
Generic Frame Rx Event 0
GDF Ring 0 Interrupt Events:
Rx Frame Drop Event 1 Generic Frame Tx Event 0
Generic Frame Rx Event 0 DMA Write Event 0
IRQ2 Event 0 IRQ1 Event 0
Int Frame Network Event 0x44
HWICRegisterOffset 0x0000 HWICRegisterErrorAddress 0x00000000
HWICRegisterTimeout 0x0000C350
TxControlFrameCounter 0x0280A9 RxControlFrameCounter 0x02657B
TxDataFrameCounter 0x000001 RxDataFrameCounter 0x000000
RegisterRWErrorCounter 0x0000 RxOverrunErrorCounter 0x0000
RxCRCErrorCounter 0x0000 RxFrameDropCounter 0x0000
TxBufferExtension 0x00 RxBufferExtension 0x00
HWICQueueBaseExtension 0x00
GDF Ring 0 Registers:
HWICQueueConfig Register 0x0007 HWICQueueBase 0x1DAD
TXQueueTailBase Register 0x4038
TxQueueBase 0x08 TxQueueTail 0x07
TxQueueSize 0x40 TxQueueHead 0x07
RxQueueHeadBase Register 0x4800
RxQueueBase 0x09 RxQueueHead 0x00
RxQueueSize 0x40 RxQueueTail 0x00
RxBufferSize 0x060C RxQueueHighWaterMark 0x00
RxQueueLowWaterMark 0x00
DMAOffsetExtension 0x00
DMAOffset 0x0000 DMAWindow 0x0000
HWICSuspResDbg Register 0x0000 HWICArbConfig Register 0x000F
GDF Ring 1 Registers:
HWICQueueConfig Register 0x0000 HWICQueueBase 0x0000
TXQueueTailBase Register 0x0000
TxQueueBase 0x00 TxQueueTail 0x00
TxQueueSize 0x00 TxQueueHead 0x00
RxQueueHeadBase Register 0x0000
RxQueueBase 0x00 RxQueueHead 0x00
RxQueueSize 0x00 RxQueueTail 0x00
RxBufferSize 0x0000 RxQueueHighWaterMark 0x00
RxQueueLowWaterMark 0x00
GDF Ring 2 Registers:
HWICQueueConfig Register 0x0000 HWICQueueBase 0x0000