
42
PE
X_nSTROBE
nERROR
X_nSTROBE
X_D1
PP_D6
X_D3
nINIT
nBUSY
X_ACKn
X_D1
X_D5
nAUTOFEED
X_D0
X_ACKn
PP_D5
PP_D2
nSELECTIN
PP_D3
PE
X_D0
nSELECTIN
X_D2
X_D6
PP_STATUS3
nAUTOFEED
SELECT
X_D4
nERROR
X_D2
nBUSY
PP_D0
PP_STATUS2
X_D3
PP_STATUS0
X_D4
PP_D1
X_D6
nINIT
PP_D7
SELECT
X_D7
X_D7
PP_D4
PP_STATUS1
X_D5
+5VD
+5VD
GND
+5VD
+5VD
TP66
TP68
RP4
1k RPACK5
2
3
4
5
6
1
TP70
RP7
22 RPACK8
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
R48
2.2k
R49
2.2k
TP67
TP69
TP71
R50
2.2k
RP3
1k RPACK5
2
3
4
5
6
1
J46
DB25M_RA
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
RP5
470 RPACK8
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
TP65
R51
2.2k
RP2
1k RPACK5
2
3
4
5
6
1
RP6
1k RPACK5
2
3
4
5
6
1
PP_CTRL0 pg(4)
PP_D[7..0] pg(4)
PP_STROBEn pg(4)
PP_CTRL1 pg(4)
PP_CTRL2 pg(4)
PP_ACKn pg(4)
PP_STATUS[3..0] pg(4)
Figure 27. UDSP - Parellel Port Interface
Summary of Contents for CS49300
Page 16: ...16 APPENDIX D SCHEMATICS Figure 6 Control and Data I O ...
Page 17: ...17 Figure 7 DSP ...
Page 18: ...18 Figure 8 External Memory ...
Page 19: ...19 Figure 9 CoDec ...
Page 20: ...20 Figure 10 External A D Converters ...
Page 21: ...21 Figure 11 L R Input Filters ...
Page 22: ...22 Figure 12 Ls Rs Input Filters ...
Page 23: ...23 Figure 13 C Sub Input Filters ...
Page 24: ...24 Figure 14 SBL SBR Input Filters ...
Page 25: ...25 Figure 15 L R Output Filters ...
Page 26: ...26 Figure 16 Ls Rs Output Filters ...
Page 27: ...27 Figure 17 C Sub Output Filters ...
Page 28: ...28 Figure 18 SBL SBR Output Filters ...
Page 29: ...29 APPENDIX E LAYOUT PLOTS GROUND PLANE VIAS ARE FLOODED Figure 19 Top Layer ...
Page 30: ...30 Figure 20 Bottom Layer ...
Page 31: ...31 Figure 21 Assembly Drawing ...
Page 50: ......