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Basic Application Download and System Configuration for PCM Pass-through
CDB48500--USB Evaluation Kit Guide
DS784DB1
©
Copyright 2008 Cirrus Logic , Inc.
4-4
Figure 4-4. Audio In via 8 Channel ADC
4.2.2.3 Audio In via USB
This feature is currently not supported.
4.2.2.4 DAI Input of CS485xx
Each of the Audio In Elements listed above are connected to a DAI element. This represent the DAI port
of the DSP. As shown in
. This dialog allows the user to set the following parameters for the
CS485xx:
•
SCLK Polarity
•
LRCLK Polarity
•
Temperature Grade - CDB48500s are populated with commercial-grade chips by default
•
Reference Clock - Set to the frequency of the crystal driving the CS485XX(Y1). This is the reference
clock is used to determine the clock dividers needed to derive Fs in ADC-only applications. If this
number changes, then all dividers for LRCLK/SCLK will change by the same ratio (e.g.
@24.576 MHz MCLK/512 = 1Fs = LRCLK, @12.288 MHz MCLK/256 = 1Fs = LRCLK.