3-5
©
Copyright 2008 Cirrus Logic , Inc.
DS784DB1
CDB48500 System Block Descriptions
CDB485x00-USB Evaluation Kit Guide
3.1.8 CS8416 S/PDIF RX
The CS8416 (U3) is a 192 kHz S/PDIF receiver with an integrated input multiplexer. The two S/PDIF input
jacks (RXP-RXN) are connected to the CS8416. Only one of the optical or coaxial S/PDIF jacks can be
used at a time and is automatically selected by the CS8416. When S/PDIF audio is being processed, the
CS8416 must master MCLK for the system (see
for details).
3.1.9 CS42448 Audio CODEC
The CS42448 (U4 and U5) is a high-performance, multi-channel audio CODEC capable of supporting
sample rates up to 192 kHz on its 6ADCs and 8 DACs. There are two of these devices on the CDB48500
and are used for all analog-to-digital and digital-to-analog conversions.
All analog inputs (AIN_1A-AIN_6B) and all analog outputs (AOUT_1A-AOUT_6B) are connected to the
CS42448s. The microphone input shares the AIN1_5 ADC with the AIN_3A RCA jack. When the
microphone is in use, the AIN_3A RCA jack is ignored.
When analog audio is being processed, the 24.576 MHz crystal for the CS485XX must master MCLK for
the system (see
for details).
3.1.10 Memory
The CDB48500 is populated with two 4 Mbit SPI flash devices and one I
2
C EEPROM. Selection from SPI
to I
2
C is changed in Software. There are 2 SPI flash footprints (U11, U13) on the board for compatibility
with both standard 8-pin serial flash pinouts. The serial control lines are shared by both footprints, and a
chip select 0 ohm jumper resistor (R101) is populated to make U13 the active device. To make U11 the
active device remove R101 and populate R110 with a 0 ohm resistor.
There is also a jumper (J105) to select Program or Normal (Run) operation of the SPI flash devices. In
program mode the CDB USB MASTER card will use the DSP_CS line to control the flash while holding
the DSP in reset with the DSP_RST line. For program mode jumper pins 2 and 3 on J105. In normal the
DSP controls the SPI device. In I
2
C mode no jumper change is required for program or normal mode of
EEPROM. For normal mode jumper pins 1 and 2. The feature to program flash from the CDB USB
MASTER is not yet supported.
3.1.11 Audio Clocking
Clocking architecture is one of the most important aspects of a digital audio system. The input and output
clock domains of the DSP must be synchronous when delivering audio data in an isochronous fashion
(constant bitrate delivery), even if the input/output domains operate at different frequencies (e.g.
48 kHz input/96 kHz output). The CDB48500 can operate in three different clocking modes. Each of these
modes is explained in the following sections.