Cirrus Logic CDB43L21, Manual

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DS723DB1 3
CDB43L21
9. ERRATA ............................................................................................................................................... 25
10. REVISION HISTORY .......................................................................................................................... 25
LIST OF FIGURES
Figure 1.General Configuration Tab ............................................................................................................ 8
Figure 2.DAC Volume Controls Tab ............................................................................................................ 9
Figure 3.Register Maps Tab - CS43L21 ................................................................................................... 10
Figure 4.Routing 1 ..................................................................................................................................... 12
Figure 5.Routing 2 ..................................................................................................................................... 12
Figure 6. Routing 3 .................................................................................................................................... 12
Figure 7.Routing 4 ..................................................................................................................................... 12
Figure 8.Routing 5 ..................................................................................................................................... 13
Figure 9.Block Diagram ............................................................................................................................. 15
Figure 10.CS43L21 and Analog I/O (Schematic Sheet 1) ........................................................................ 16
Figure 11.S/PDIF I/O (Schematic Sheet 2) ............................................................................................... 17
Figure 12.FPGA (Schematic Sheet 3) ....................................................................................................... 18
Figure 13.Level Shifters & I/O Stake Header (Schematic Sheet 4) .......................................................... 19
Figure 14.Control Port I/O (Schematic Sheet 5) ....................................................................................... 20
Figure 15.Power (Schematic Sheet 6) ...................................................................................................... 21
Figure 16.Silk Screen ................................................................................................................................ 22
Figure 17.Top-Side Layer ......................................................................................................................... 23
Figure 18.Bottom-Side Layer .................................................................................................................... 24
LIST OF TABLES
Table 1. MCLK and Clock/Data Routing Options ...................................................................................... 11
Table 2. CS43L21 H/W Mode Control ....................................................................................................... 11
Table 3. System Connections ................................................................................................................... 14
Table 4. Jumper Settings .......................................................................................................................... 14