Cirrus Logic CDB43L21 Page 13 Manual Download | Manualshive

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DS723DB1

13

CDB43L21

Figure 8. Routing 5

MCLK

LRCK/SCLK

SDIN

CS43L21

I/O Header

MCLK

LRCK/SCLK

SDIN

CS8415

RMCK

(256Fs)

OLRCK/

OSCLK

SDOUT

(LJ)

Oscillator

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Summary of Contents for CDB43L21

Page 1: ...valuate the CS43L21 in Software Mode System timing can be provided by the CS8415 by the CS43L21 with supplied master clock or by an I O stake header with a DSP connected RCA phono jacks are provided for the CS43L21 analog outputs 1 8th inch jacks are also available for head phone output Digital data input is available via RCA phono or optical connectors to the CS8415 The Windows software provides ...

Page 2: ...TIONS 14 5 JUMPER SETTINGS 14 6 CDB43L21 BLOCK DIAGRAM 15 7 CS43L21 SCHEMATICS 16 8 CDB43L21 LAYOUT 22 9 ERRATA 25 10 REVISION HISTORY 25 1 SYSTEM OVERVIEW 4 1 1 Power 4 1 2 Grounding and Power Supply Decoupling 4 1 3 FPGA 4 1 4 CS43L21 4 1 5 CS8415 Digital Audio Receiver 5 1 6 Oscillator 5 1 7 I O Stake Headers 5 1 8 Analog Outputs 5 1 9 Stand Alone Switches 6 1 10 Control Port Connectors 6 1 10 ...

Page 3: ...Figure 10 CS43L21 and Analog I O Schematic Sheet 1 16 Figure 11 S PDIF I O Schematic Sheet 2 17 Figure 12 FPGA Schematic Sheet 3 18 Figure 13 Level Shifters I O Stake Header Schematic Sheet 4 19 Figure 14 Control Port I O Schematic Sheet 5 20 Figure 15 Power Schematic Sheet 6 21 Figure 16 Silk Screen 22 Figure 17 Top Side Layer 23 Figure 18 Bottom Side Layer 24 LIST OF TABLES Table 1 MCLK and Cloc...

Page 4: ...of the connections to the CS43L21 Figure 16 on page 22 shows the component placement Figure 17 on page 23 shows the top layout and Figure 18 on page 24 shows the bottom layout The decoupling ca pacitors are located as close to the CS43L21 as possible Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise 1 3 FPGA The FPGA provides digital signal routin...

Page 5: ...on J5 and a control port header CS43L21 S W Control The serial port header pro vides access to the serial audio signals required to interface with a DSP Figure 13 on page 19 Selections are made in the control port of the FPGA accessible through the General Configurations tab of the Cirrus FlexGUI software or through the on board FPGA H W Control switches Section 2 Software Mode Con trol on page 7 ...

Page 6: ...g easy manipulation of each register This GUI interfaces with the CDB via the RS 232 connector and controls all Software Mode options Section 2 Software Mode Control on page 7 provides a description of the GUI 1 10 1 USB Connector Connecting a USB port cable from a PC to the USB connector and launching the Cirrus FlexGUI software enables one to use the CDB43L21 1 10 2 RS 232 Connector Connecting a...

Page 7: ...by clicking on the Update button The default state of all registers are now visible 7 Engage and then disengage the Power Down push button in the General Configurations group This per forms the necessary write sequence to the CS43L21 for Software Mode operation For standard setup 8 Set up the signal routing in the General Configurations tab as desired 9 Set up the CS43L21 in the General Configurat...

Page 8: ... outlined below CS43L21 Basic Configuration Includes basic register controls in the CS43L21 used for setting up power status interface format and clocking functions See Section 2 2 and Section 2 3 for more controls in the CS43L21 S PDIF Receiver Control Includes all available Hardware Mode controls for setting up the CS8415 Clock Data Routing and CS43L21 Reset Includes controls used for routing cl...

Page 9: ...ion of each register is included in the CS43L21 data sheet Digital Volume Control Includes all digital volume controls and adjustments for the DAC Analog Multipliers Includes the control for the analog gain of the output amplifier and displays the full scale output factors Limiter Configuration Includes all configuration settings for the Limiter Tone Control Includes all bass and treble boosting c...

Page 10: ...dual register settings Register values can be modified bit wise or byte wise For bit wise click the appropriate push button for the desired bit For byte wise the desired hex value can be typed directly into the register address box in the register map The FPGA and GPIO tabs may be ignored Figure 3 Register Maps Tab CS43L21 ...

Page 11: ... Reserved 01 I O Header MCLK I O Header clocks data route through FPGA 10 Oscillator MCLK I O Header clocks data route through FPGA 11 Reserved Signal Routing S 3 0 General Description Detailed Description CS8415 MCLK 1 Figure 4 0000 CS8415 Clocks Data 1 CS8415 masters MCLK 2 CS8415 masters PCM clocks 3 CS8415 data into SDIN I O MCLK 2 Figure 5 0100 I O Clocks Data 1 I O masters MCLK 2 I O masters...

Page 12: ...ader MCLK LRCK SCLK SDIN CS8415 RMCK 256Fs OLRCK OSCLK SDOUT LJ Figure 4 Routing 1 Figure 5 Routing 2 Oscillator MCLK LRCK SCLK SDIN CS43L21 I O Header MCLK LRCK SCLK SDIN CS8415 RMCK 256Fs OLRCK OSCLK SDOUT LJ Figure 6 Routing 3 Figure 7 Routing 4 Routing 2 Reserved Oscillator MCLK LRCK SCLK SDIN CS43L21 I O Header MCLK LRCK SCLK SDIN CS8415 RMCK 256Fs OLRCK OSCLK SDOUT LJ ...

Page 13: ...DS723DB1 13 CDB43L21 Figure 8 Routing 5 MCLK LRCK SCLK SDIN CS43L21 I O Header MCLK LRCK SCLK SDIN CS8415 RMCK 256Fs OLRCK OSCLK SDOUT LJ Oscillator ...

Page 14: ... voltage for the VL supply Note 1 1 8 V Voltage source is 1 8 V regulator 2 5 V Voltage source is 2 5 V regulator 3 3 V Voltage source is 3 3 V regulator J36 VA_HP Selects source of voltage for the VA_HP supply 1 8 V Voltage source is 1 8 V regulator 2 5 V Voltage source is 2 5 V regulator J25 VA Selects source of voltage for the VA supply 1 8 V Voltage source is 1 8 V regulator 2 5 V Voltage sour...

Page 15: ...BLOCK DIAGRAM Figure 9 Block Diagram Analog Output Line Headphone Software Mode Control Port CS43L21 S PDIF Input CS8415 Clocks Data Header I C SPI Header FPGA Oscillator socket Reset MCLK Reset Reset MCLK Reset Hardware Mode Switches ...

Page 16: ...16 DS723DB1 CDB43L21 7 CS43L21 SCHEMATICS Figure 10 CS43L21 and Analog I O Schematic Sheet 1 ...

Page 17: ...DS723DB1 17 CDB43L21 Figure 11 S PDIF I O Schematic Sheet 2 ...

Page 18: ...18 DS723DB1 CDB43L21 Figure 12 FPGA Schematic Sheet 3 ...

Page 19: ...DS723DB1 19 CDB43L21 Figure 13 Level Shifters I O Stake Header Schematic Sheet 4 ...

Page 20: ...20 DS723DB1 CDB43L21 Figure 14 Control Port I O Schematic Sheet 5 ...

Page 21: ...DS723DB1 21 CDB43L21 Figure 15 Power Schematic Sheet 6 ...

Page 22: ...22 DS723DB1 CDB43L21 8 CDB43L21 LAYOUT Figure 16 Silk Screen CDB43L21 CS43L21 CS43L21 CS43L21 ...

Page 23: ...DS723DB1 23 CDB43L21 Figure 17 Top Side Layer ...

Page 24: ...24 DS723DB1 CDB43L21 Figure 18 Bottom Side Layer ...

Page 25: ...owns the copyrights associated with the information contained herein and gives con sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus This consent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale CER...

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