8
DS723DB1
CDB43L21
2.1
General Configuration Tab
The “General Configuration” tab provides high-level control of signal routing on the CDB43L21. This tab also
includes basic controls for the CS43L21 for quickly setting up the CDB43L21 in simple configurations. Sta-
tus text detailing the CS43L21’s specific configuration is shown in parenthesis or appears directly below the
associated control. This text may change depending on the setting of the associated control. A description
of each control group is outlined below:
CS43L21 Basic Configuration
- Includes basic register controls in the CS43L21 used for setting up power
status, interface format and clocking functions. See
for more controls in the
CS43L21.
S/PDIF Receiver Control
- Includes all available Hardware Mode controls for setting up the CS8415.
Clock/Data Routing and CS43L21 Reset
- Includes controls used for routing clocks and data between the
CS43L21, CS8415, oscillator and the I/O stake header. Also includes a reset control for the CS43L21.
Update -
Reads all registers in the FPGA and CS43L21 and reflects the current values in the GUI.
Reset
- Resets FPGA to default routing configuration.
Figure 1. General Configuration Tab
Summary of Contents for CDB43L21
Page 16: ...16 DS723DB1 CDB43L21 7 CS43L21 SCHEMATICS Figure 10 CS43L21 and Analog I O Schematic Sheet 1 ...
Page 17: ...DS723DB1 17 CDB43L21 Figure 11 S PDIF I O Schematic Sheet 2 ...
Page 18: ...18 DS723DB1 CDB43L21 Figure 12 FPGA Schematic Sheet 3 ...
Page 19: ...DS723DB1 19 CDB43L21 Figure 13 Level Shifters I O Stake Header Schematic Sheet 4 ...
Page 20: ...20 DS723DB1 CDB43L21 Figure 14 Control Port I O Schematic Sheet 5 ...
Page 21: ...DS723DB1 21 CDB43L21 Figure 15 Power Schematic Sheet 6 ...
Page 22: ...22 DS723DB1 CDB43L21 8 CDB43L21 LAYOUT Figure 16 Silk Screen CDB43L21 CS43L21 CS43L21 CS43L21 ...
Page 23: ...DS723DB1 23 CDB43L21 Figure 17 Top Side Layer ...
Page 24: ...24 DS723DB1 CDB43L21 Figure 18 Bottom Side Layer ...
