24
DS851DB1
CDB42L56
-5
+5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
+0
+0.5
+1
+1.5
+2
+2.5
+3
+3.5
+4
+4.5
d
B
r
A
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-40
+40
-35
-30
-25
-20
-15
-10
-5
+0
+5
+10
+15
+20
+25
+30
+35
d
B
r
A
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
Figure 24.
Freq. Response - Digital In to HP Out
Figure 25.
Fade-to-Noise Linearity- Digital In to HP Out
-100
-60
-98
-96
-94
-92
-90
-88
-86
-84
-82
-80
-78
-76
-74
-72
-70
-68
-66
-64
-62
d
B
r
A
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-100
-60
-98
-96
-94
-92
-90
-88
-86
-84
-82
-80
-78
-76
-74
-72
-70
-68
-66
-64
-62
d
B
r
A
-120
+0
-100
-80
-60
-40
-20
dBFS
Figure 26. THD+N vs. Freq. - Digital In to Line Out
Figure 27.
THD+N vs. Amplitude - Digital In to Line Out
Summary of Contents for CDB42L56
Page 28: ...28 DS851DB1 CDB42L56 8 CDB42L56 SCHEMATICS Figure 35 CS42L56 Analog I O Schematic Sheet 1 ...
Page 29: ...DS851DB1 29 CDB42L56 Figure 36 S PDIF Digital Interface Schematic Sheet 2 ...
Page 30: ...30 DS851DB1 CDB42L56 Figure 37 PLL oscillator and external I O connections Schematic Sheet 3 ...
Page 31: ...DS851DB1 31 CDB42L56 Figure 38 Microcontroller and FPGA Schematic Sheet 4 ...
Page 32: ...DS851DB1 32 CDB42L56 Figure 39 Power Schematic Sheet 5 ...
Page 33: ...DS851DB1 33 CDB42L56 9 CDB42L56 LAYOUT Figure 40 Silk Screen ...
Page 34: ...DS851DB1 34 CDB42L56 Figure 41 Top Side Layer ...
Page 35: ...DS851DB1 35 CDB42L56 Figure 42 GND Layer 2 ...
Page 36: ...DS851DB1 36 CDB42L56 Figure 43 Power Layer 3 ...
Page 37: ...DS851DB1 37 CDB42L56 Figure 44 Bottom Side Layer ...
