Cirrus Logic CDB42L56 Manual Download Page 18

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DS851DB1

CDB42L56

5. JUMPER SETTINGS AND SYSTEM CONNECTIONS

CONNECTOR

REF

INPUT/OUTPUT

SIGNAL PRESENT

EXT. +5V

TP9

Input

+5V power supply for evaluation board

GND

TP10

Input

GND reference from power supply

Ext. Input

TP6

Input

+4.5V external power supply for buck converter

GND

TP7

Input

GND reference from power supply

AAA

BT1
BT2
BT3

Input
Input
Input

Socket for +1.5 V AAA batteries for buck converter

RS232

J95

Input/Output

RS232 serial port connection to PC for I²C control port signals

USB I/O

J94

Input/Output

USB connection to PC for I²C control port signals

S/PDIF Optical IN

OPT3

Input

CS8416 digital audio input via optical cable

S/PDIF Optical OUT

OPT2

Output

CS8406 digital audio output via optical cable

S/PDIF COAX IN

J61

Input

CS8416 digital audio input via coaxial cable

S/PDIF COAX OUT

J68

Output

CS8406 digital audio input via coaxial cable

MICRO RESET

Input

Reset for microcontroller (U84)

CS42L56 RESET

Input

Reset for CS42L56 (U3)

FPGA Program

Input

Reload Xilinx program into the FPGA from Flash (U14)

FPGA JTAG

J75

Input/Output

I/O for programming the FPGA (U5)

MICRO JTAG

J110

Input/Output

I/O for programming the microcontroller (U84)

AP PSIA Transmitter

J78

Input/Output

Digital Data and Clocks to CS42L56

AP PSIA Receiver

J40

Input/Output

Digital Data and Clocks from CS42L56

AIN1B
AIN1A
AIN2B
AIN2A
AIN3B
AIN3A

J14
J10
J21
J18
J23
J24

Input
Input
Input
Input
Input
Input

RCA connectors for analog inputs to CS42L56

AIN1
AIN2
AIN3

J22
J13

Input
Input
Input

Stereo jacks for analog inputs to CS42L56

HP Channel A
HP Channel B

J38
J37

Output
Output

RCA connector for headphone analog output from CS42L56

Line Channel A
Line Channel B

J15
J17

Output
Output

RCA connector for line analog output from CS42L56

HP Stereo Connection

Output

Stereo jack for headphone stereo output from CS42L56

Oscillator

Input

Oscillator for providing master clock for system timing

I/O Header

J104

Input/Output

I/O for Clocks and Data

S/W CONTROL

J109

Input/Output

I/O for external I²C control port signals

Test Points

TP1-TP2,

TP34-TP36,

TP11-TP16,

TP23, TP25,

TP26, TP28

Outputs

Test Points for monitoring signals to and from CS42L56

Table 2. System Connections

Summary of Contents for CDB42L56

Page 1: ...e appli cations Use of the board requires an analog digital signal source an analyzer and power supplies A Windows PC com patible computer is also needed in order to configure the CS42L56 and the board System timing can be provided by the CS8416 on board by the CS42L56 supplied with a master clock by the on board crystal oscillator or via an I O stake header with a DSP connected RCA phono connecto...

Page 2: ...b 15 4 5 Codec Analog Output Volume Tab 16 4 6 Register Maps Tab 17 5 JUMPER SETTINGS AND SYSTEM CONNECTIONS 18 6 PERFORMANCE PLOTS 21 7 CDB42L56 BLOCK DIAGRAM 27 8 CDB42L56 SCHEMATICS 28 9 CDB42L56 LAYOUT 33 10 REVISION HISTORY 38 LIST OF FIGURES Figure 1 Quick Start Board Layout 8 Figure 2 S PDIF In to Analog Out and Analog In to S PDIF Out 9 Figure 3 PSIA In to Analog Out and Analog In to PSIA ...

Page 3: ...5 Figure 29 FFT Crosstalk Digital In to Line Out 0 dBFS 25 Figure 28 FFT Digital In to Line Out 0 dBFS 25 Figure 29 FFT Digital In to Line Out 60 dBFS 25 Figure 30 FFT Digital In to Line Out No Input 25 Figure 31 FFT Digital In to Line Out No Input Wideband 25 Figure 32 Freq Response Digital In to Line Out 26 Figure 33 Fade to Noise Linearity Digital In to Line Out 26 Figure 34 Block Diagram 27 Fi...

Page 4: ...tor For a detailed explanation on software controls refer to Section 4 on page 11 Alternatively the I C interface to the CS42L56 can be directly accessed through an I O header J109 to accept external timing and signals in a user application during system development 1 2 Power Power is supplied to the evaluation board through either the 5 0 V test points or the VBUS supply from the USB NOTE The min...

Page 5: ... the CS8406 is made using controls in the Board Configuration tab of the Cirrus FlexGUI software Section 3 Configuration Options on page 9 and Section 4 Software Mode Control on page 11 provide configuration examples and software details 1 4 2 CS8421 Sample Rate Converter Rx SRC from CS42L56 The CS8421 Rx SRC receives PCM digital audio data from the CS42L56 and synchronizes this data with either t...

Page 6: ...voltage levels must be selected cautiously since the lines between the headers and the device are not buffered Please refer to the CS42L56 product data sheet for a detailed explanation on digital I O interface specifications Selections are made using the Board Configuration tab of the Cirrus FlexGUI software Section 4 on page 11 provides software configuration details 1 9 CS42L56 Audio Codec A com...

Page 7: ... is inserted in J1 Headers J12 and J4 can be used to select optional 16 or 32 resistive loads for headphone outputs Headers J2 and J3 give users the option of receiving filtered or unfiltered outputs on the RCA headphone output jacks Figure 35 on page 28 illustrates how the analog outputs are connected and routed Table 3 on page 19 pro vides details on jumper selections for filtered or unfiltered ...

Page 8: ... 3 V and VCP VLDO and VA to 1 8 V J48 J53 J52 J74 J7 and J11 should be shunted Set Board Power setting to USB Left pins on J109 and J104 should be shunted Provide digital inputs to the board either through the S PDIF optical or RCA phono connectors or through the PSIA I O header J78 Receive digital outputs from the board either through the S PDIF optical or RCA phono connectors or through the PSIA...

Page 9: ... S PDIF input must be provided as the S PDIF Tx CS8406 uses the RMCK signal from the S PDIF Rx CS8416 for synchronization in this configuration as shown in the Figure 2 Line Output B A HP Output J21 32 32 16 16 J4 J12 B A AIN1A AIN1B AIN2A AIN2B AIN3A AIN3B J19 J20 LRCK CS42L56 SCLK SDIN SLAVE MCLK SDOUT LINEOUTB LINEOUTA HPOUTB HPOUTA AIN1A AIN1B AIN2A AIN2B AIN3A AIN3B S PDIF Rx CS8416 RX LRCK R...

Page 10: ...hat a 24 000 MHz on board oscillator is populated in Y1 Line Output B A HP Output J21 32 32 16 16 J4 J12 B A AIN1A AIN1B AIN2A AIN2B AIN3A AIN3B J19 J20 LRCK CS42L56 SCLK SDIN SLAVE MCLK SDOUT LINEOUTB LINEOUTA HPOUTB HPOUTA AIN1A AIN1B AIN2A AIN2B AIN3A AIN3B FPGA PLL Divider Divider Divider On Board Oscillator Tx SRC CS8421 SLAVE ISCLK ILRCK SDIN OSCLK OLRCK SDOUT XTI PSIA Tx J78 TX SCLK TX LRCK...

Page 11: ...e Update button The default state of all registers are now visible For standard set up 5 Set up the signal routing in the Board Configuration tab as desired 6 Set up the CS42L56 in the Codec Configuration Codec Analog Input Volume Codec DSP Engine Co dec Analog Output Volume and Register Maps tabs as desired 7 Begin evaluating the CS42L56 For quick set up the CDB42L56 may alternatively be configur...

Page 12: ...9 provides details on some quick setup configurations FPGA Routing Includes controls to setup the FPGA for using the S PDIF or the PSIA test interface and for setting up clock and signal routing for CS42L56 in master slave mode This group also has controls for se lecting SCLK and LRCK frequencies perform divide operations on the oscillator CS8416 S PDIF Receiver Control Controls for the CS8416 CS8...

Page 13: ...control A description of each control group is outlined below See the CS42L56 data sheet for complete register descriptions Power Control Controls for powering all devices ADC Input Configuration Controls for input configuration and routing mixing Serial Port Configuration Controls for all settings related to the serial I O data and clocks on the board Status Displays status of interrupt bits Upda...

Page 14: ... setting of the associated control A description of each control group is outlined below Digital Volume Control Digital volume controls and adjustments ADC output ALC Configuration Configuration settings for the Automatic Level Control ALC Analog Volume Control Analog volume controls and adjustments for the PGA and MIC amps Noise Gate Configuration Configuration settings for the noise gate Update ...

Page 15: ...hange depending on the setting of the associated control A description of each control group is out lined below Digital Volume Control Controls for mutes or inverts and the volume gain of the ADC mix or the PCM mix Tone Control Controls for the corner frequencies and the volume gain of the treble and bass shelving fil ters Beep Generator Controls for setting the on off time frequency volume mix an...

Page 16: ...ge pump frequency and adaptive power supply mode for the class H control to determine the appropriate power supply for the HP Line amplifiers Headphone Line Amplifiers Controls for configuring mutes and for setting the volume of the signal from the headphone line amplifier and controls for the HP Line mux Limiter Configuration settings for the peak detect and limiter in the CS42L56 Master Volume C...

Page 17: ...es can be modified bit wise or byte wise Left clicking on a particular register accesses that register and shows its contents at the bottom The user can change the register con tents by using the push buttons by selecting a particular bit and typing in the new bit value or by selecting the register in the map and typing in a new hex value Figure 9 Register Maps Tab CS42L56 ...

Page 18: ...ilinx program into the FPGA from Flash U14 FPGA JTAG J75 Input Output I O for programming the FPGA U5 MICRO JTAG J110 Input Output I O for programming the microcontroller U84 AP PSIA Transmitter J78 Input Output Digital Data and Clocks to CS42L56 AP PSIA Receiver J40 Input Output Digital Data and Clocks from CS42L56 AIN1B AIN1A AIN2B AIN2A AIN3B AIN3A J14 J10 J21 J18 J23 J24 Input Input Input Inpu...

Page 19: ...ference to GND SHUNTED AIN2REF and RCAs for AIN2A and AIN2B given a board ground reference OPEN AIN2REF is given AIN2A and AIN2B ground ref erence on RCA shield J7 Shunt to RCA Provides RCA reference to GND SHUNTED AIN1REF and RCAs for AIN1A and AIN1B given a board ground reference OPEN AIN1REF is given AIN1A and AIN1B ground ref erence on RCA shield J5 1 8 V Buck Input Selects power supply source...

Page 20: ... unfiltered output for HPOUTB 2 4 1 3 Unfiltered output selected for HPOUTB 4 6 3 5 RC filtered output selected for HPOUTB J34 Board Power Selects source of Board Power 1 2 Board powered from external 5 V source con nected to TP9 TP10 2 3 Board powered from USB J16 Tri state I O Tri states FGPA I O SHUNTED FGPA I O pins are tri stated OPEN FGPA I O pins in normal operation Default factory settings...

Page 21: ...r capacitor values yield significant improvement in THD N at low frequencies Fig 10 shows the THD N vs frequency performance measured with several FILT ca pacitor values 100 60 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 d B F S 20 20k 50 100 200 500 1k 2k 5k 10k Hz 100 60 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 d B F S 120 20 100 80 60 40 dBr Figure 10 THD N vs Freq ...

Page 22: ...3 5 4 4 5 d B F S 20 20k 50 100 200 500 1k 2k 5k 10k Hz 40 40 35 30 25 20 15 10 5 0 5 10 15 20 25 30 35 d B F S 140 0 120 100 80 60 40 20 dBr T TTT T T T T T Figure 16 Freq Response Analog In to Digital Out Figure 17 Fade to Noise Linearity Analog In to Digital Out 100 60 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 100 60 98 96 94 92 90 88...

Page 23: ... 0 130 120 110 100 90 80 70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 130 120 110 100 90 80 70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 20 FFT Digital In to HP Out 60 dBFS Figure 21 FFT Digital In to HP Out No Input 140 0 130 120 110 100 90 80 70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 130 120 110 100 90 80 70 ...

Page 24: ...dBFS Figure 24 Freq Response Digital In to HP Out Figure 25 Fade to Noise Linearity Digital In to HP Out 100 60 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 100 60 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 d B r A 120 0 100 80 60 40 20 dBFS Figure 26 THD N vs Freq Digital In to Line Out Figure 27 THD N vs Amplitude Digital In...

Page 25: ...S 140 0 130 120 110 100 90 80 70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 140 0 130 120 110 100 90 80 70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 28 FFT Digital In to Line Out 0 dBFS Figure 29 FFT Digital In to Line Out 60 dBFS 140 0 130 120 110 100 90 80 70 60 50 40 30 20 10 d B r A 20k 120k 40k 60k 80k 100k Hz 140 0 130 120 110 100 90 80 70 60...

Page 26: ...1 1 5 2 2 5 3 3 5 4 4 5 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz 40 40 35 30 25 20 15 10 5 0 5 10 15 20 25 30 35 d B r A 140 0 120 100 80 60 40 20 dBFS Figure 32 Freq Response Digital In to Line Out Figure 33 Fade to Noise Linearity Digital In to Line Out ...

Page 27: ... USB µ controller CS42L56 S PDIF Rx CS8416 S PDIF Tx CS8406 FPGA Oscillator socket I2 C Interface Reset Reset PLL Tx SRC CS8421 Analog Outputs Line Headphone Analog Inputs Line MIC External System I O Header Rx SRC CS8421 PSIA I O Header USB RS232 S PDIF Dout S PDIF Din ...

Page 28: ...28 DS851DB1 CDB42L56 8 CDB42L56 SCHEMATICS Figure 35 CS42L56 Analog I O Schematic Sheet 1 ...

Page 29: ...DS851DB1 29 CDB42L56 Figure 36 S PDIF Digital Interface Schematic Sheet 2 ...

Page 30: ...30 DS851DB1 CDB42L56 Figure 37 PLL oscillator and external I O connections Schematic Sheet 3 ...

Page 31: ...DS851DB1 31 CDB42L56 Figure 38 Microcontroller and FPGA Schematic Sheet 4 ...

Page 32: ...DS851DB1 32 CDB42L56 Figure 39 Power Schematic Sheet 5 ...

Page 33: ...DS851DB1 33 CDB42L56 9 CDB42L56 LAYOUT Figure 40 Silk Screen ...

Page 34: ...DS851DB1 34 CDB42L56 Figure 41 Top Side Layer ...

Page 35: ...DS851DB1 35 CDB42L56 Figure 42 GND Layer 2 ...

Page 36: ...DS851DB1 36 CDB42L56 Figure 43 Power Layer 3 ...

Page 37: ...DS851DB1 37 CDB42L56 Figure 44 Bottom Side Layer ...

Page 38: ... copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus This consent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONA...

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