Cirrus Logic ARM CDB89712, User Manual

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DS502UM2 ix
LIST OF TABLES
Table 2-1. Terms and Definitions ................................................................................................. 2-2
Table 2-2. Units of Measurement................................................................................................. 2-3
Table 4-1. Jumper settings Used to Enable Certain Processor States ........................................ 4-4
Table 4-2. Flash Memory Interface Settings ................................................................................ 4-6
Table 4-3. Description of Momentary Switches............................................................................ 4-6
Table 4-4. LED Indicators ............................................................................................................ 4-7
Table 4-5. Memory Map for the CS89712 Microcontroller, Booting Ice_boot .............................. 4-8
Table 4-6. Memory Map for the CS89712, Booting Angel ........................................................... 4-8
Table 4-7. GPIO Assignments for the CS89712 Development Board ......................................... 4-9
Table 4-8. Interrupt Assignments for the CS89712 Development Board .................................... 4-9
Table 4-9. Toggle Switch Assignments...................................................................................... 4-10
Table 4-10. Power Management Switches ................................................................................ 4-10
Table 4-11. Power States of the CS89712’s Peripherals by Operating State ............................ 4-11
Table 6-1. Description of Connectors........................................................................................... 6-1
Table 6-2. Serial Port GPIO Implemented Connections .............................................................. 6-2
Table 6-3. Serial Port Logic Level Header (JP34)........................................................................ 6-2
Table 6-4. Serial Port Control Jumper Assignments .................................................................... 6-2
Table 6-5. Header Assignments................................................................................................... 6-4
Table 6-6. Expansion Interface .................................................................................................... 6-4