Cirrus Logic ARM CDB89712, User Manual

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CDB89712
6-4 DS502UM2
6.3.4 Headers
Table 6-5 describes the headers for the CS89712 Development Board.
6.3.5 Expansion Interface
This expansion interface is intended to support the addition of small add-on boards. The interface
exposes sufficient signals to allow byte-wide interfacing to peripheral devices. It should be noted
that the interface is 3.3V only.
For a detailed explanation of this interface refer to the CS89712 Data Sheet .
Location Name Description
JP21 MULTI-ICE Connection to Multi-ICE or Wiggler
JP24 MULTI-ICE Connection to Multi-ICE.
JP34 TTL SERIAL PORT 1 TTL connection to Serial Port 1
JP19, JP20,
JP22, JP23
Expansion headers for
user defined options Refer to schematic for details on header pin assignments.
JP15 RS232 EN-DIS Enable / disable Serial Port 1
JP31 TTL/SER2 TTL I/O for Serial Port 1
JP27-30 CPU CONFIG Configures CPU clock speed and boot operation.
J4-7 PROCESSOR PINS Intended for future product development. In future, this
board may be manufactured with the processor depopu-
lated and a separate processor carrier board dropped onto
these sites.
Table 6-5. Header Assignments
Description Pin No. Pin No. Description
D0 1 2 V
DD
(3.3V)
D1 3 4 A0
D2 5 6 A1
D3 7 8 A2
D4 9 10 A3
D5 11 12 nMWE (Write Enable)
D6 13 14 nEXTFIQ (Interrupt)
D7 15 16 PD1 (GPIO)
nCS5 (Chip Select) 17 18 GND
nMOE (Output Enable) 19 20 GND
Table 6-6. Expansion Interface