DSB75 Development Support Board Rev. B1 Hardware Description
Confidential / Released
DSB75_hd_v12
Page 53 of 96
2008-08-26
3.11 Serial Peripheral Interfaces
The Serial Peripheral Interface (SPI) system consists of one master device and one or more
slave devices.
The master is defined as a microcomputer providing the SPI clock, and the slave as any
integrated circuit receiving the SPI clock from the master. The GSM module always operates
as a master device in master-slave operation mode.
The SPI has a 4-wire synchronous serial interface. Data communication is enabled with a
low active Slave Select or Chip Select wire (CS). Data are transmitted with a 3-wire interface
consisting of wires for serial data input (DI), serial data output (DO) and serial clock (SCLK).
The GSM module may provide two different SPI interfaces available alternatively to the I²C-,
and ASC1- lines (depending on software configuration). On the DSB75, they are available on
the 10 pin X510 pin header.
In order to use the SPI interfaces some switches have to be set (see Figure 27).
The logic voltage VDD is available at the X510 pin header for the supply of the external SPI
device driver.
Table 22: Alternative configuration of SPI interface lines
SPI interfaces
Alternative interfaces
CS1
DI1
DO1 I2CDAT
SPI1
SCLK1
I2C
I2CCLK
CS2 TXD1
DI2 RXD1
DO2 CTS1
SPI2
SCLK2
ASC1
RTS1
Figure 27 shows the simplified interface schematic.
Figure 28 shows the placement of the SPI related switches and the pin location.
Electrical characteristics are specified in section 8.
1
3
TXD1
RXD1
RTS1
CTS1
S300
S302
S304
S306
31
29
51
53
CS2
DI2
SCLK2
DO2
1
3
5
7
1
3
SPICS
SPIDI
I2CCLK
I2CDAT
S456
S457
S500
S501
75
7
11
70
CS1
DI1
SCLK1
DO1
2
4
6
8
B2B
X100
10 pin
X510
4
4
44
4
SPI2
SPI1
GND
10
VDD
VDD
9
Figure 27: SPI interfaces
