Cinterion DSB75, Hardware Description

Page: 89 / 96

DSB75 Development Support Board Rev. B1 Hardware Description
Confidential / Released
DSB75_hd_v12 Page 89 of 96 2008-08-26
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06
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.20
04
SCHE
M
A
T
IC
ASC
2
AS
C
0
9pol S ubD
R2
4
4
22
0R
DSB7
5
9pol Sub D
ASC
1
9pol SubD
T
O
P HI
ER
ARCHY
L
EVE
L
1:
1
B1
S2
00
1
2
3
LY
T
679
-C
O
V2
44
2
1
V2
00
BC
8
47
B1
25
B2
6
C1
C2
3 1
E1
4
E2
5 6 7 8 9
22
0R
R2
4
3
22
0R
X2
02
1 2 3 4
100K
R251
22
0R
R2
36
R2
37
L2
01
60
0R
/10
0M
H
Z
22
0R
R2
01
V2
42
LY
T
679
-C
O
21
C207
100N
R2
67
100
K
22
0R
R2
35
C231
100K
R264
R2
05
220
R
100N
LY
T
6
79
-C
O
21
R2
4
0
22
0R
C2
00
10
0N
GN
D
3V
0
22
0R
R2
4
1
V2
34
LS
T
6
79
-C
O
V2
35
21
R2
02
220
R
GN
D
V2
40
LS
T
679
-C
O
21
2
20R
R2
1
2
10
T4
O
U
T
17
T5
IN
T
5
O
U
T
12 27
V+
V-
4
26
VCC
V2
39
LG
T
679
-C
O
21
VDD
R3
IN
11
18
R3
OU
T
S
HDN
14
T1
IN
24
T1
O
U
T
5
23
T2
IN
6
T2
O
U
T
T3
IN
22
T3
O
U
T
7
T4
IN
19
C1
-
25
C2
+
1 3
C2
-
13
EN
GND
2
15
MB
A
U
D
R1
IN
8
21
R1
OU
T
R1
OU
T
B
16
9
R2
IN
R2
OU
T
20
GN
D
GN
D
3V
0
GN
D
D2
0
1
M
A
X3
23
7E
C
A
I
28
C1
+
C211
33P
NB_
100
N
C2
08
VD
D
2 3 4 5 6 7 8 9
3V
0
GND
A B
C D
E F
3V
0
X2
05
1
V2
43
LS
T
679
-C
O
21
3V
0
R2
2
0
0R
R2
0
3
22
0R
100N
C230
C202
GND
2
20R
R2
1
1
T4
IN
19
10
T4
O
U
T
17
T5
IN
T
5
O
U
T
12 27
V+
V-
4
26
VCC
100N
9
R2
IN
R2
OU
T
20
R3
IN
11
18
R3
OU
T
S
HDN
14
T1
IN
24
T1
O
U
T
5
23
T2
IN
6
T2
O
U
T
T3
IN
22
T3
O
U
T
7
28
C1
+
C1
-
25
C2
+
1 3
C2
-
13
EN
GND
2
15
MB
A
U
D
R1
IN
8
21
R1
OU
T
R1
OU
T
B
16
60
0R
/10
0M
H
Z
22
0R
R2
3
8
D2
0
0
M
A
X3
23
7E
C
A
I
3V
0
60
0R
/10
0M
H
Z
L2
03
3V
0
L2
02
GND
R270
10K
R2
4
2
22
0R
22
0R
R2
33
R250
47K
G
F E D C B A
4K7
R252
GN
D
1
00N
C2
05
LG
T
6
79
-C
O
V2
30
21
GN
D
R2
34
22
0R
GN
D
22
0R
R2
09
10 20
VC
C
C2
06
1
00N
R2
32
22
0R
2A
2
2A
3
15 17
2A
4
19
2O
E
9
2Y
1
7
2Y
2
5
2Y
3
3
2Y
4
GN
D
1A
3
8
1A
4
1
1O
E
18
1Y
1
16
1Y
2
14
1Y
3
12
1Y
4
11
2A
1
13
22
0R
SN
74
LV
C
244
A
D
220
2
1A
1
4
1A
2
6
GN
D
GN
D
GND
LS
T
679
-C
O
V2
41
21
R2
13
LG
T
679
-C
O
V2
38
21
R246
33R
22
0R
R2
10
R2
0
0
22
0R
2
X206
1 2
R2
63
10
0K
0R
R2
14
X204
1
21
GN
D
LY
T
6
79
-C
O
V2
33
21
10
0N
R2
0
7
22
0R
V2
37
LS
T
6
79
-C
O
C210 NB_
V2
32
LG
T
6
79
-C
O
21
GND
C2
0
3
V2
31
LG
T
6
79
-C
O
21
R2
06
220
R
33P
GN
D
S2
01
1
2
3
C2
0
9
10
0N
10
0N
C2
0
4
100
K
R2
66
3V
0
2O
E
9
2Y
1
7
2Y
2
5
2Y
3
3
2Y
4
GN
D
10 20
VCC
1Y
1
16
1Y
2
14
1Y
3
12
1Y
4
11
2A
1
13
2A
2
2A
3
15 17
2A
4
19
SN
74
LV
C
24
4A
D2
21
2
1A
1
4
1A
2
6
1A
3
8
1A
4
1
1O
E
18
100K
R262
22
0R
R2
30
6
5
4
3
2
1
100K
R260
R261
100K
10U
C232
3V0
3V
0
10
9
8
7
AP
PR
'D
US
ER
DA
T
E
R2
0
8
2
20R
3V
0
Si
em
e
ns
A
G
22
0R
R2
0
4
R2
31
22
0R
4 5 6 7 8 9
GND
X203
1 2
3V
0
X2
01
1 2 3
V2
36
21
R2
3
9
22
0R
GN
D
R2
21
0R
C2
01
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LS
T
6
79
-C
O
R2
7
2
10
0K
3V0
0R
R2
15
10
0N
D
CD0
RX
D1
_I
RX
D2
_
I
CTS
1
_I
SY
N
C
DT
R0
ASC _EN 1
DT
R0
TX
D2
_I
ASC _E N2
AS
C
_
SD
AS
C
_
S
D
DT
R
VD
D
_
EN
PW
R
_I
N
D
100K
R271
GND
RX
D1
RT
S
1
PW
R
_I
N
D
RX
D2
_G
P
IO
9
TX
D2
_
G
P
IO
1
0
RT
S
0
CT
S
0
DC
D0
TX
D1
_I RI
NG
0
DS
R0
RX
D
0
_I
RT
S
1
_I
CT
S
1
US
C2
TX
D0
_
I
US
C1
RX
D0
_
I
RX
D0
TX
D0
TX
D0
_I
TX
D1
PW
R
_I
N
D
AS
C
_
S
D
ASC
_
E
N
1
AS
C
_
EN
2
RI
NG
0
RX
D
0_
I
T
X
D
0_I
CT
S
0
RT
S
0
DS
R
0
NB
=
not
m
ount
e
d
Figure 52: Schematic sheet 2 – ASC0, ASC1 and ASC2 interface