DSB75 Development Support Board Rev. B1 Hardware Description
Confidential / Released
DSB75_hd_v12
Page 54 of 96
2008-08-26
S110
X5
10
X5
11
X5
51
X5
52
S307
S305
S303
S301
S300S302S304S306
S713S712
S717S716
X101
X102
S201
S200
X554
X703
X561
X560
X562
S5
04
S5
03
S5
02
S5
01
S5
00
S4
57
S4
52
S4
56
S4
55
S4
53
S4
54
S4
50
S4
60
S4
51
S4
61
S4
62
S4
64
S4
65
S4
63
S4
66
S4
69
S4
59
S4
67
S4
58
S4
68
1
10
39
40
1
2
1
1
39
40
1
2
1
1
1
2
2
9
10
9 10
2
9
1
3
Figure 28: SPI interfaces location and related switches
Table 23: Pin assignment of the SPI interfaces X510
X510
pin
Name
I/O
Description
X100 signal
name
Config.
switches
Remark
1
CS2
O
Chip select 2
TXD1
S300:1
2
CS1
O
Chip select 1
SPICS
S456:1
3
DI2
I
Data in 2
RXD1
S302:1
4
DI1
I
Data in 1
SPIDI
S457:1
5 SCLK2 O
Clock
2
RTS1
S304:1
6 SCLK1 O
Clock
1
I2CCLK
S500:1
7
DO2
O
Data out 2
CTS1
S306:1
8
DO1
O
Data out 1
I2CDAT
S501:1
9
VDD
O
2.9V supply out
10 GND
