JXT6966 / JXTS6966 Technical Reference
CHASSIS PLANS
v
P
OWER
C
ONNECTION
The PICMG
®
1.3 specification supports soft power control signals via the Advanced Configuration and
Power Interface (ACPI). The JXT6966/JXTS6966 supports these signals, controlled by the ACPI and are
used to implement various sleep modes. When control signals are implemented, the type of ATX or EPS
power supply used and the operating system software will dictate how system power should connect to the
SHB. It is critical that the correct method be used. Refer to
- Power Connection
section in the JXT manual
to determine the method that will work with your specific system design. The
Advanced Setup
chapter in
the manual contains the ACPI BIOS settings.
PCI
E
XPRESS
2.0
L
INKS AND
PICMG®
1.3
B
ACKPLANES
The PCI Express® links on the JXT6966 connect directly to the processors. These links can operate as
either PCI Express 2.0 or PCI Express 1.1 links based on the end-point devices on the backplane that are
connected to the SHB. In addition to automatically configuring themselves for either PCIe 2.0 or PCIe 1.1
operations, the links also configure themselves for either graphics or server-class operations. In other
words, the multiple x4 links from the processors (links A0, A1, A2 and A3) can be combined into a single
x16 PCIe electrical link or multiple x8 links on a backplane. The CPU’s x4 links can train down to x1
links, but cannot bifurcate into multiple x1 links. The PCIe link (B0) from the board’s PCH has a x4
default configuration and can be made to bifurcate into four, x1 PCIe links with a factory modification to
the JXT board. Contact Chassis Plans if you require this B0 link configuration change. An optional
PEX10 module connected to a dual-processor JXT6966 provides more backplane links than are currently
supported in the PICMG 1.3 specification. This JXT6966 capability provides additional PCI Express
bandwidth and option card support in the system design. Refer to the
PCI Express®
Reference
chapter and
to
Appendix C - PCI Express Backplane Usage
of this manual for more information.
PICMG
1.3
B
ACKPLANE
I/O
The JXT6966 and JXTS6966 enable the following PICMG 1.3 backplane I/O connectivity via the SBC’s
edge connector C:
Four USB 2.0 interfaces
One 10/100Base-T Ethernet interface
PICMG
1.3
B
ACKPLANE
C
LASSIFICATION
The JXT6966 and JXTS6966 are system host boards that can operate as either a Server or Graphics-Class
PICMG 1.3 SHB. The JXT SHBs are essentially combo-class boards because of the capabilities of the PCI
Express links built into the SHB’s processors. Chassis Plans recommends using a combo-class PICMG 1.3
backplane such as the Chassis Plans BPC7009 or BPC7041 with the SHBs in order to ensure the use of all
available backplane option card slots. See
Appendix C, PCI Express Backplane Usage
for more details.
O
FF
-B
OARD
V
IDEO
C
ARD
U
SAGE
If the system design requires an off-board video card, then the card must be placed in a backplane slot
driven with PCI Express links from the JXT6966’s first processor. This is an Aptio® 4.x BIOS limitation
that may be corrected in future software revisions. Listed below are the acceptable BPC7009 and BPC7041
backplane slots for use with an off-board video card:
BPC7009 - Card slot PCIe1, PCIe2 or PCIe3
BPC7041 - Card slot PCIe6, PCIe7, PCIe8, PCIe9 or PCIe10
BIOS
The JXT6966 and JXTS6966 feature the Aptio® 4.x BIOS from American Megatrends, Inc. (AMI) with a
ROM-resident setup utility called the Aptio Text Setup Environment or TSE. Details of the Aptio TSE are
provided in the separate
JXT6966 / JXTS6966 BIOS Technical Reference
manual.
F
OR
M
ORE
I
NFORMATION
For more information on any of these features, refer to the appropriate sections
JXT6966 / JXTS6966
Hardware Technical Reference Manual
. The BIOS and hardware technical reference manuals are available
under the
Downloads
tab on the JXT6966 or JXTS6966 web pages.
