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Chassis Plans JXT6966, Hardware Technical Reference

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Chassis Plans JXT6966 Hardware Technical Reference Download Page 65

JXT6966 / JXTS6966 Technical Reference 

 

BIOS Messages 

 

 

A-9 

 

CHASSIS PLANS  

0xB8 – 0xBF  Reserved for future AMI codes 
0xC0 – 0xCF  OEM BDS initialization codes 

DXE Error Codes 

0xD0 

CPU initialization error 

0xD1 

North Bridge initialization error 

0xD2 

South Bridge initialization error 

0xD3 

Some of the Architectural Protocols are not available 

0xD4 

PCI resource allocation error. Out of Resources 

0xD5 

No Space for Legacy Option ROM 

0xD6 

No Console Output Devices are found 

0xD7 

No Console Input Devices are found 

0xD8 

Invalid password 

0xD9 

Error loading Boot Option (LoadImage returned error) 

0xDA 

Boot Option is failed (StartImage returned error) 

0xDB 

Flash update is failed 

0xDC 

Reset protocol is not available 

 

 

DXE Beep Codes 

 

# of Beeps 

Description 

4 

Some of the Architectural Protocols are not available 

5 

No Console Output Devices are found 

5 

No Console Input Devices are found 

1 

Invalid password 

6 

Flash update is failed 

7 

Reset protocol is not available 

8 

Platform PCI resource requirements cannot be met 

 

 

Summary of Contents for JXT6966

Page 1: ...JXT6966 JXTS6966 S6966 xxx Revision A HARDWARE TECHNICAL REFERENCE Intel Xeon C5500 series Quad Core PROCESSOR BASED SHB...

Page 2: ...arising out of or in connection with the performance or use of the product or information provided Chassis Plans liability shall in no event exceed the purchase price of the product purchased hereunde...

Page 3: ...al Computer Manufacturers Group PCI Express is a trademark of the PCI SIG All other brand and product names may be trademarks or registered trademarks of their respective companies LIABILITY DISCLAIME...

Page 4: ...This page intentionally left blank...

Page 5: ...nterfaces 1 9 Serial ATA 300 Ports 1 9 Power Fail Detection 1 10 Battery 1 10 Power Requirements 1 10 Temperature Environment 1 11 Mechanical 1 11 Board Stiffener Bars 1 11 UL Recognition 1 11 Configu...

Page 6: ...agram 5 3 IOB33 S7015 xxx I O Plate Diagram 5 3 IOB33 Connectors 5 4 IOB33 Connectors continued 5 5 PEX10 Overview 5 7 APPENDIX A BIOS MESSAGES A 1 Introduction A 1 Aptio Boot Flow A 1 BIOS Beep Codes...

Page 7: ...d yourself frequently by touching the metal chassis of the system before handling any components The system must be plugged into an outlet that is connected to an earth ground Use antistatic padding o...

Page 8: ...Populating the memory sockets with Mini DIMMs having different speeds is supported on the SHB however the overall memory interface speed will run at the speed of the slowest Mini DIMM Populate the mem...

Page 9: ...tion This JXT6966 capability provides additional PCI Express bandwidth and option card support in the system design Refer to the PCI Express Reference chapter and to Appendix C PCI Express Backplane U...

Page 10: ...JXT6966 JXTS6966 Technical Reference vi CHASSIS PLANS This page intentionally left blank...

Page 11: ...CPU2 on the JXT6966 provides four additional x4 PCI Express 2 0 or 1 1 links to a backplane via an optional plug in card called the Chassis Plans PEX10 These extra links provide added bandwidth to sys...

Page 12: ...nes of PCI Express for off board system integration Direct DDR3 1333 Memory Interfaces into the Intel Xeon C5500 Processors Six DDR3 Mini DIMM sockets capable of supporting up to 192GB of system memor...

Page 13: ...JXT6966 JXTS6966 Technical Reference Specifications 1 3 CHASSIS PLANS JXT6966 S6966 xxx Dual Processor SHB Block Diagram...

Page 14: ...Specifications JXT6966 JXTS6966 Technical Reference CHASSIS PLANS 1 4 JXT6966 S6966 xxx Dual Processor SHB Layout Diagram...

Page 15: ...JXT6966 JXTS6966 Technical Reference Specifications 1 5 CHASSIS PLANS JXTS6966 S6966 xxx Single Processor SHB Block Diagram...

Page 16: ...Specifications JXT6966 JXTS6966 Technical Reference CHASSIS PLANS 1 6 JXTS6966 S6966 xxx Single Processor SHB Layout Diagram...

Page 17: ...dual processor JXT6966 the first CPU connects to the PCH and the second CPU feeds its information to the PCH via the first CPU s DMI link Memory Interface Three DDR3 1333MHz memory channels per proces...

Page 18: ...same interface speed All memory modules must have gold contacts Low voltage DDR3L Mini DIMMs are not supported The SHB supports the following memory module memory latency timings o 6 6 6 for 800MHz DD...

Page 19: ...es are on board 10 100 1000Base T Ethernet interfaces located on the board s I O bracket and implemented using an Intel 82575EB Gigabit Ethernet Controller These I O bracket interfaces support Gigabit...

Page 20: ...5500 Quad Core EC5549 JXT6966 Dual CPU 2 53GHz 1 07A 6 48A 4 44A Intel Xeon C5500 Quad Core EC5549 JXTS6966 Single CPU 2 53GHz 0 71A 3 28A 2 10A Intel Xeon C5500 Dual Core EC5539 JXT6966 Dual CPU 2 27...

Page 21: ...densing Mechanical The standard cooling solution used on the JXT6966 and JXTS6966 SHBs enables placement of option cards approximately 2 75 69 85mm away from the top component side of the SHB Contact...

Page 22: ...tions such as changing the PCI Express link bifurcation operation Contact Chassis Plans tech support before installing this jumper to prevent any unintended system operation JU8 Password Clear two pos...

Page 23: ...ection or a category 3 CAT3 or higher UTP 2 pair cable for a 10 Mb s network connection A category 5e CAT5e or higher UTP 2 pair cable is recommended for a 1000 Mb s Gigabit network connection Status...

Page 24: ...f On 1 Off Off Off On 2 Off Off On Off 2 Off Off On Off 3 Off Off On On 3 Off Off On On 4 Off On Off Off 4 Off On Off Off 5 Off On Off On 5 Off On Off On 6 Off On On Off 6 Off On On Off 7 Off On On On...

Page 25: ...nal 1 Gnd 2 12V 3 FanTach Notes 1 P2 is the fan connector of CPU2 and P19 is for CPU1 P4A P4B 10 100 1000Base T Ethernet Connectors LAN1 LAN2 Dual RJ 45 connector Pulse JG0 0024NL Each individual RJ 4...

Page 26: ...Bus USB Connector 10 pin dual row header Molex 702 46 1001 5V fused with self resetting fuses Pin Signal Pin Signal 1 5V USB2 2 5V USB3 3 USB2 4 USB3 5 USB2 6 USB3 7 Gnd USB2 8 Gnd USB3 9 NC 10 NC P17...

Page 27: ...or Molex 67491 0031 Pin Signal 1 Gnd 2 TX 3 TX 4 Gnd 5 RX 6 RX 7 Gnd Notes 1 P27 SATA0 interface P28 SATA1 interface P31 SATA2 interface P32 SATA3 interface P35 SATA4 interface P36 SATA5 interface 2 S...

Page 28: ...H_RCIN 15 ICH_SIOPME 16 ICH_A20GATE 17 Gnd 18 Gnd 19 L_FRAME 20 L_AD3 21 L_DRQ1 22 L_AD2 23 L_DRQ0 24 L_AD1 25 SERIRQ 26 L_AD0 27 Gnd 28 Gnd 29 PCLK14SIO 30 PCLK33LPC 31 Gnd 32 Gnd 33 SMBDATA_RESUME 3...

Page 29: ...26 P1_PE_RXP6 27 P1_PE_TXN6 28 P1_PE_RXN6 29 P1_PE_TXP7 30 P1_PE_RXP7 31 P1_PE_TXN7 32 P1_PE_RXN7 33 P1_PE_CFG0 34 P1_GEN2_DSBL 35 P1_PE_CGF1 36 P1_PE_CFG2 37 NC 38 NC 39 NC 40 NC 41 P1_PE_TXP8 42 P1_...

Page 30: ...Specifications JXT6966 JXTS6966 Technical Reference CHASSIS PLANS 1 20 This page intentionally left blank...

Page 31: ...ts than PCI bus connectors The PCIe connectors are physically different based on the number of lanes in the connector PCI Express Links Several PCI Express channels lanes can be bundled for each expan...

Page 32: ...combo class SHBs that support either PCI Express server class or graphics class backplane configurations Server applications require multiple high bandwidth PCIe links and therefore the server class...

Page 33: ...nted must be located on edge connector C of the SHB The SHB makes the Intelligent Platform Management Bus IPMB signals available to the user The SHB supports four USB ports USB 4 5 6 and 7 and one 10...

Page 34: ...3V 14 B_PE_TXN0 GND 14 A_PE_TXN1 0 GND 14 S5_TXN GND 14 CLKA CLKB 15 GND B_PE_RXP0 15 GND A_PE_RXP1 0 15 GND S5_RXP 15 3 3V GND 16 GND B_PE_RXN0 16 GND A_PE_RXN1 0 16 GND S5_RXN 16 AD31 PME 17 B_PE_T...

Page 35: ...D4 GND 47 GND A_PE_RXP0 47 12V 12V 47 3 3V 3 3V 47 GND AD2 48 GND A_PE_RXN0 48 12V 12V 48 3 3V 3 3V 48 AD3 AD1 49 A_PE_TXP1 GND 49 12V 12V 49 3 3V 3 3V 49 AD0 GND 50 A_PE_TXN1 GND 50 3 3V 3 3V 51 GND...

Page 36: ...nt from SHB slot through the x8 PCIe connector B to the target device s Clock synchronization of PCIe expansion slots PCIe fundamental reset A and B A A A SHB Backplane SHB Backplane SHB SHB Backplane...

Page 37: ...quipped with a PEX10 expansion slot The Chassis Plans BPC7009 and BPC7041 backplane feature this PEX10 option slot A PEX10 routes the additional PCIe links available from the JXT6966 s second processo...

Page 38: ......

Page 39: ...ultiple pins capable of delivering the current necessary to power high performance processors The PICMG 1 3 specification supports soft power control signals via the Advanced Configuration and Power I...

Page 40: ...bled PICMG 1 3 system The following table shows the required connections that must be made for soft power control to work Signal Description Source 12 DC voltage for those systems that require it Powe...

Page 41: ...5VSB Not Required Power Supply PWRGD Not Required Power Supply PSON Power Supply On This signal is used to turn on an ATX or EPS type power supply If an ATX or EPS power supply is used in this legacy...

Page 42: ...Power Connection JXT6966 JXTS6966 Technical Reference CHASSIS PLANS 3 4 This page intentionally left blank...

Page 43: ...kplane in order to support high end PCI Express graphics and video cards Graphics class SHB configurations also provide as many lower bandwidth x1 or x4 links as possible A combo class configuration i...

Page 44: ...communication with the SHB host device The first figure shows a server class SHB the second shows a graphics class SHB PCI Express link configuration straps for each PCI Express option card slot on a...

Page 45: ...or a JXTS 6966 single processor SHB with a particular backplane Chassis Plans continuously adds backplanes to our product line so contact us or visit our website for the latest backplane availability...

Page 46: ...PCI Express Backplane Usage JXT6966 JXTS6966 Technical Reference CHASSIS PLANS 4 4...

Page 47: ...JXT6966 JXTS6966 Technical Reference PCI Express Backplane Usage 4 5 CHASSIS PLANS This page intentionally left blank...

Page 48: ......

Page 49: ...le for use by the system designer Two RS232 communication ports One Floppy drive interface One Parallel printer interface One PS 2 Mini DIN connector for PS 2 keyboard and mouse connections Also inclu...

Page 50: ...se keyboard mini DIN on the I O bracket PS 2 mouse keyboard parallel port and floppy drive connectors PCI Express expansion capability for use with PCI Express backplanes Compatible with PCI Industria...

Page 51: ...JKXT6966 JXTS6966 Technical Reference I O Expansion Boards 5 3 CHASSIS PLANS IOB33 S7015 xxx Layout Diagram IOB33 S7015 xxx I O Plate Diagram...

Page 52: ...t Ready I 2 Receive Data I 7 Request to Send O 3 Transmit Data O 8 Clear to Send 4 Data Terminal Ready O 9 Ring Indicator I 5 Signal Gnd P3 PS 2 Mouse and Keyboard Connector 6 pin mini DIN Kycon KMDG...

Page 53: ...Data Bit 3 10 Gnd 11 Data Bit 4 12 Gnd 13 Data Bit 5 14 Gnd 15 Data Bit 6 16 Gnd 17 Data Bit 7 18 Gnd 19 ACK 20 Gnd 21 Busy 22 Gnd 23 Paper End 24 Gnd 25 Slct 26 NC P7 Keyboard Header 5 pin single ro...

Page 54: ...1 L_DRQ1 22 L_AD2 23 L_DRQ0 24 L_AD1 25 SERIRQ 26 L_AD0 27 Gnd 28 Gnd 29 PCLK14SIO 30 PCLK33LPC 31 Gnd 32 Gnd 33 SMBDATA_RESUME 34 IPMB_DAT 35 SBMCLK_RESUME 36 IPMB_CLK 37 SALRT _RESUME 38 IPMB_ALRT 3...

Page 55: ...is a passive board that mounts to the back of a Chassis Plans JXT6966 This PEX10 passive interface card routes the four additional PCIe 2 0 x4 electrical links from second processor on a JXT6966 down...

Page 56: ...I O Expansion Boards JXT6966 JXTS6966 Technical Reference CHASSIS PLANS 5 8 This page intentionally left blank...

Page 57: ...which may apply to various status code descriptions Security SEC initial low level initialization Pre EFI Initialization PEI memory initialization1 Driver Execution Environment DXE main hardware initi...

Page 58: ...s of Beeps Description 4 Some of the Architectural Protocols are not available 5 No Console Output Devices are found 5 No Console Input Devices are found 1 Invalid password 6 Flash update is failed 7...

Page 59: ...2 3 4 5 6 and 7 These LED are located on the top of the SHB just above the board s battery socket The POST Code LEDs and are numbered from right position 1 LED0 to left position 8 LED7 The POST code c...

Page 60: ...Power on Reset type detection soft hard 0x2 AP initialization before microcode loading 0x3 North Bridge initialization before microcode loading 0x4 South Bridge initialization before microcode loadin...

Page 61: ...emory initialization Memory presence detection 0x2D Memory initialization Programming memory timing information 0x2E Memory initialization Configuring memory 0x2F Memory initialization other 0x30 Rese...

Page 62: ...Progress Codes 0xE0 S3 Resume is stared S3 Resume PPI is called by the DXE IPL 0xE1 S3 Boot Script execution 0xE2 Video repost 0xE3 OS S3 wake vector call 0xE4 0xE7 Reserved for future AMI progress c...

Page 63: ...zation 0x69 North Bridge DXE initialization is started 0x6A North Bridge DXE SMM initialization is started 0x6B North Bridge DXE initialization North Bridge module specific 0x6C North Bridge DXE initi...

Page 64: ...0x9C USB Detect 0x9D USB Enable 0x9E 0x9F Reserved for future AMI codes 0xA0 IDE initialization is started 0xA1 IDE Reset 0xA2 IDE Detect 0xA3 IDE Enable 0xA4 SCSI initialization is started 0xA5 SCSI...

Page 65: ...for Legacy Option ROM 0xD6 No Console Output Devices are found 0xD7 No Console Input Devices are found 0xD8 Invalid password 0xD9 Error loading Boot Option LoadImage returned error 0xDA Boot Option i...

Page 66: ...p state 0x30 System is waking up from the S3 sleep state 0x40 System is waking up from the S4 sleep state 0xAC System has transitioned into ACPI mode Interrupt controller is in PIC mode 0xAA System ha...

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