User manual for APPEB1012 Revision 1.2, Oct 2019
Solar Energy Harvesting Supercapacitor Evaluation Board using a
PMIC with MPPT
© CAP-XX Pty Limited 2019 | Tel +61 2 9420 0690 | www.cap-xx.com
Page
4
of
11
C8, C9 are landing pads for CAP-XX GY cylindrical cells and C10 are the landing pads a CAP-XX
prismatic single cell or dual cell part. R7 is a 1
Ω
resistor designed to allow the input current to be
measured, while R14 is a 1
Ω
resistor for measuring the output current. If the voltage drop caused
by 1
Ω
resistors is too large, they can be replaced with a lower value resistor or shorted via a link
across the jumpers labelled Isolar and Iload. Note these links could be wire loops to enable the use
of a current probe to measure the current.
JP3, labelled OUTPUT selects whether the output is directly connected to the supercapacitor (DIR)
or controlled by the PMIC (CTRL). When the direct output is chosen on JP3 output control PFETs
M3 & M5 are bypassed and M3, M4, and M5 are OFF only drawing ~200nA leakage current. When
the output control is selected, the output is gated by back-back PFETs M3 and M5. The upper and
lower thresholds of the output enable are set in the system configuration such that the PMIC
enables the output when the voltage reaches Vchrdy and disables it approximately 400ms after the
voltage drops below Vovdis. When the supercapacitor voltage is
≥
Vchrdy, the PMIC turns M4 on
which in turn switches M3 & M5 ON, connecting the output to the supercapacitor. When the
supercapacitor discharges below Vovdis, the PMIC waits 400ms before turning M4 OFF which
turns OFF M3 & M5, disabling the output and allowing the supercapacitor to charge.
The dual LDO outputs, HVOUT and LVOUT, are also enabled by the charge management
thresholds Vchrdy and Vovdis. This is internally controlled by the PMIC.
Figure 1. Schematic of APPEB1012
