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 User manual for APPEB1012 Revision 1.2, Oct 2019 

Solar Energy Harvesting Supercapacitor Evaluation Board using a 
PMIC with MPPT 

© CAP-XX Pty Limited 2019  |  Tel +61 2 9420 0690  |  www.cap-xx.com 

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Status Pins 

Users are also given access to the STATUS[2:0] logic output levels on the status pins if required.  

The  status  pin  STATUS[0]  turns  high  when  the  supercapacitor  voltage  reaches  Vchrdy  to  signal 
that the LDOs are operational and can be enabled.  

If  the  supercapacitor  voltage  gets  discharged  below  Vovdis,  the  LDOs  are  gated  OFF  and  the 
boost converter on the AEM10941 is no longer supplied by the storage element to protect it from 
further discharge. When Vscap drops below Vovdis STATUS[1] changes from low to high, to warn 
that  the  system  will  soon  shut  down,  and  ~600ms  later,  when  shutdown  occurs,  STATUS[1]  and 
STATUS[0] both go from high to low. This is illustrated in figure 10. 

 

Figure 10: Example STATUS pin operation

 

The  status  of  the  MPP  controller  is  reported  with  one  dedicated  status  pin  (STATUS[2]).    The 
status pin is asserted when the input is set open circuit to measure V

OC

 of the energy harvester. 

Further Information

 

CAP-XX will be pleased to provide further information on the applications described here, and on 
the use of supercapacitors in any application. Please use the contact details provided on the CAP-
XX web site (

www.cap-xx.com

). 

 
This user manual is available on the CAP-XX web site. On the web site you may also find product 
bulletins,  datasheets,  SPICE  models,  application  white  paper,  application  briefs  and  design-aid 
calculator (

http://cap-xx.com/resources/resources.htm

). 

  

Summary of Contents for APPEB1012

Page 1: ...uation Board using a PMIC with MPPT CAP XX Pty Limited 2019 Tel 61 2 9420 0690 www cap xx com Page 1 of 11 Evaluation board user manual APPEB1012 User Manual for APPEB1012 Solar Energy Harvesting Supe...

Page 2: ...with Open circuit voltage sensing for MPPT every 5s Configurable MPPT with 2 pin programming Selectable Vppt Voc ratio of 70 75 85 90 Vin operation from 50mV to 4 5V Configurable cell voltage control...

Page 3: ...xternal resistors that can be used to set these voltages to other values The output of the board can be either directly connected to a load or controlled by the PMIC The PMIC enables the output when t...

Page 4: ...supercapacitor DIR or controlled by the PMIC CTRL When the direct output is chosen on JP3 output control PFETs M3 M5 are bypassed and M3 M4 and M5 are OFF only drawing 200nA leakage current When the...

Page 5: ...CAP XX prismatic dual cells are installed in the same direction Please ensure that the active balance configuration header is connected to the cell midpoint as shown in red in figure 3 below Figure 3...

Page 6: ...eader must be connected to GND as shown in red on the left of figure 5 When 2 CAP XX cylindrical supercapacitors are connected as dual cells both supercapacitors should be fitted with their correct po...

Page 7: ...e LDO outputs one high and one low voltage are accessible from the LVOUT and HVOUT headers with voltages Vlv and Vhv respectively to supply circuits that require a stable voltage If enabled LVOUT and...

Page 8: ...rs that set custom mode All six configuration resistors shown in Figures 6 and 7 must be installed as follows Vovch Vchrdy and Vovdis are defined by R2 R3 R5 and R6 If we define the total resistor RT...

Page 9: ...reshold voltages to be different from the PMIC inbuilt options Table 4 Example resistor values for typical use Output mode selection APPEB1012 has two output modes either directly connect the output t...

Page 10: ...e 3 Custom external resistors were chosen to create the charge management equal to the first row of table 4 In this example Vovch 2 7 Vchrdy 2 57V Vovdis 2 2V and a constant current of 100mA was drawn...

Page 11: ...1 changes from low to high to warn that the system will soon shut down and 600ms later when shutdown occurs STATUS 1 and STATUS 0 both go from high to low This is illustrated in figure 10 Figure 10 Ex...

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