Canon ZR60 A, Service Manual

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ZR70 MC A, ZR65 MC A, ZR60 A
CHAPTER 2. TECHNICAL DESCRIPTION
2-13
4-3 Recorder Signal Processing
< VIC3 >IC2301
• The VIC, MI-COM, DIF INTERFACE and USB INTERFACE circuits are integrated on a single semiconductor chip.
• A/B DATA : Input in camera mode. B DATA is output and A DATA is input at playback. (MACS digital effect circuit is used
at playback.)
The video data and signals input to VIC3 are subjected to digital VCR format signal processing. Audio data,
subcode data and ITI data are also created at VIC3, and these signals are output to VRP2 as 41.85 Mbps data of
DV format.
• DIF : After conversion to digital data conforming to IEEE1394 standard, the data is output at DV terminal. At digital
input, the data enters VIC3 signal processing circuit via the opposite route.
< VRP2 >IC2000
Recording data of 41.85 Mbps output from VIC3 is amplified at VRP2, and is recorded on magnetic tape while undergoing head
switching of CH-1, CH-2 with a switching pulse. At playback, the head output signal is amplified and sent to VIC3.
< VIF2 >IC2100
Y and C signals sent from VIC3 are output as Y, C signals for S terminal and composite video.
At line input, input signals undergo level adjustment, sync signal separation and are output to VIC3.
Fig. 2-10
AV JACK
S TERMINAL
CVF
LCD
LCD
IC1102
MACS
VIDEO
INTERFACE
A DATA
B DATA
R,G,B
D/A A/D
IC2303
SDRAM
REC/PB
PROCESS
IC2100
VIF2
ECC
COMPRESSION
/DEMOD.
BUS
IC2301
VIC3
VIC BLOCK DIF BLOCK
MI-COM. BLOCK
SDRAM
INTERFACE
DIF
INTERFACE
FR MI-COM.
USB BLOCK
USB INTERFACE
AUDIO
INTERFACE
IC2000
VRP2
DV
TERMINAL
USB
TERMINAL
AV
JACK
IC801
AIF3
VIDEO
HEAD