12
Reg. 00
Status
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Write
Read-only
Read
Reserved
INIT
MPS
FIFOE FIFOF
INT
INIT
Init Status (1 = initialized since last power up, 0 = not initialized since last power up)
MPS
Multiplexer Size (0 = 16 to 1 multiplexer, 1 = dual 8 to 1 multiplexer, see note)
FIFOE
FIFO Empty Status (1 = FIFO currently empty, up to 8 writes available and not busy)
FIFOF
FIFO Full Status (1 = FIFO currently full, additional writes are lost)
INT
Interrupt Status (if enabled; 1 = interrupt line asserted, 0 = interrupt line not asserted)
Note:
The multiplexer size is controlled by the jumper discussed in Section 3.2.1. This bits indicates
the configuration of the jumper.
Reg. 02
Control
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Write
Reserved
TM
DPE
STE
INTE
RST
Read
Reserved
TM
DPE
STE
INTE
RST
TM
Timer Mode (proper operation is guaranteed only for the time = 8ms)
0 0
8ms
0 1
2ms
1 0
4ms
1 1
64ms
DPE
Driver Power Enable (1 = enables power to relay drivers, 0 = removes power)
STE
Self-Test Enable (1 = disable power to all row & column drivers and allows testing the
operation of the FIFO without causing relay movement, 0 = allows row & column drivers
to be powered (if driver power is enabled). Be sure the FIFO is empty before returning
this bit to 0.
INTE
Interrupt Enable (1 = enables interrupts, 0 = disables interrupts)
RST
Reset (1 = initiates a soft reset, 0 = releases module from reset condition)
Figure 5. I/O Registers
C&H Technologies, Inc. <> 445 Round Rock West Drive <> Round Rock, Texas 78681 <> www.chtech.com
Summary of Contents for M 2 2 0
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